Abstract: An image scaling processor is disclosed comprising a multi-pixel vertical scaler and a multiline horizontal scaler. The multi-pixel vertical scaler includes a plurality of convolvers that convolve a plurality of pixels in parallel with a vertical kernel comprising weights to generate vertically scaled pixels. The multiline horizontal scaler includes horizontal scaling circuits configured to receive vertically scaled pixels from respective line stores, wherein a given horizontal scaling circuit comprises an input configured to receive one vertically scaled pixel at a time, a pipeline of convolver stages configured to, at each stage, convolve vertically scaled pixels with respective horizontal kernel coefficients. The pipeline transfers pixels from a last convolver stage of the pipeline to a second memory, wherein the pixels from the last convolver stage of the pipeline are horizontally and vertically scaled, wherein the pixels stored in the second memory are arranged to be displayed as a scaled image.