Abstract: The present disclosure presents a circuit, a method, and a system to drive a half-bridge switch using depletion (D) mode compound semiconductor (III-V) switching transistors for a DC-DC converter using at least one driver to drive the switches of the circuit. Also included is at least one charge pump electrically connected to a gate of the transistor, to maintain a voltage that holds the transistor in an off-state. The circuit includes AC coupling capacitors to level shift a voltage and realize fast transistor switching.

Abstract: The present disclosure presents a circuit, a method, and a system to drive a half-bridge switch using depletion (D) mode compound semiconductor (III-V) switching transistors for a DC-DC converter using at least one driver to drive the switches of the circuit. Also included is at least one charge pump electrically connected to a gate of the transistor, to maintain a voltage that holds the transistor in an off-state. The circuit includes AC coupling capacitors to level shift a voltage and realize fast transistor switching.

Abstract: The present disclosure presents a circuit, a method, and a system to drive a half-bridge switch using depletion (D) mode compound semiconductor (III-V) switching transistors for a DC-DC converter using at least one driver to drive the switches of the circuit. Also included is at least one charge pump electrically connected to a gate of the transistor, to maintain a voltage that holds the transistor in an off-state. The circuit includes AC coupling capacitors to level shift a voltage and realize fast transistor switching.

Abstract: A voltage converter including a buck converter and a capacitive voltage divider. The converter includes four capacitors, a switch circuit, an inductor and a controller. A first capacitor is coupled between a reference node and a first output node which develops a first output voltage. A second capacitor is coupled between an input node and either the reference node or the first output node. The switch circuit couples a third capacitor between the reference and first output nodes in a first state of a PWM signal, and couples the third capacitor between the first output and input nodes in a second PWM signal state. The inductor is coupled to the third capacitor and provides a second output node coupled to the fourth capacitor providing a second output voltage. The controller controls the duty cycle of the PWM signal to regulate the second output voltage to a predetermined level.

Abstract: A pulse control clock generator for a voltage regulator including a comparator, a window circuit, a filter circuit, a ramp circuit, and a current circuit. The comparator compares a ramp voltage with a compensation voltage and provides a corresponding pulse control signal. The compensation voltage is indicative of output voltage error. The window circuit adds a window voltage to the compensation voltage to provide a hysteretic voltage. The filter circuit filters the hysteretic voltage to provide a filtered hysteretic voltage, such that a difference between the compensation voltage and the filtered hysteretic voltage is reduced in response to a load increase. The ramp circuit provides a repetitive ramp voltage which ramps between the filtered hysteretic voltage and the compensation voltage based on the pulse control signal. The current circuit increases a slope of the ramp voltage in response to the load increase.

Abstract: A pulse control clock generator for a voltage regulator including a comparator, a window circuit, a filter circuit, a ramp circuit, and a current circuit. The comparator compares a ramp voltage with a compensation voltage and provides a corresponding pulse control signal. The compensation voltage is indicative of output voltage error. The window circuit adds a window voltage to the compensation voltage to provide a hysteretic voltage. The filter circuit filters the hysteretic voltage to provide a filtered hysteretic voltage, such that a difference between the compensation voltage and the filtered hysteretic voltage is reduced in response to a load increase. The ramp circuit provides a repetitive ramp voltage which ramps between the filtered hysteretic voltage and the compensation voltage based on the pulse control signal. The current circuit increases a slope of the ramp voltage in response to the load increase.

Abstract: A voltage converter including a capacitive voltage divider combined with a buck converter and battery charger. The converter includes four capacitors, a switch circuit, an inductor and a controller. The capacitors form a capacitor loop between an input node and a reference node and include a fly capacitor controlled by the switch circuit, which is controlled by a PWM signal to half the input voltage to provide a first output voltage on a first output node, and to convert the first output voltage to the second output voltage via the inductor. The controller controls the PWM signal to regulate the second output voltage, and provides a voltage control signal to control the input voltage to maintain the first output node between a predetermined minimum and maximum battery voltage levels. A battery charge path is coupled to the reference node and battery charge mode depends upon the battery voltage.

Abstract: A voltage converter including a buck converter and a capacitive voltage divider. The converter includes four capacitors, a switch circuit, an inductor and a controller. A first capacitor is coupled between a reference node and a first output node which develops a first output voltage. A second capacitor is coupled between an input node and either the reference node or the first output node. The switch circuit couples a third capacitor between the reference and first output nodes in a first state of a PWM signal, and couples the third capacitor between the first output and input nodes in a second PWM signal state. The inductor is coupled to the third capacitor and provides a second output node coupled to the fourth capacitor providing a second output voltage. The controller controls the duty cycle of the PWM signal to regulate the second output voltage to a predetermined level.

Abstract: A power switching stage architecture for a buck topology-based, DC—DC converter includes an upper power switching N-channel device FET integrated in the same semiconductor circuit chip with the switching driver, while a lower power switching is also an N-channel FET, but is external to the driver chip. Either of the two power switching FETs may be configured to include a pilot FET cell, to facilitate current sensing for the controller.

Abstract: A power switching stage architecture for a buck topology-based, DC-DC converter includes an upper power switching N-channel device FET integrated in the same semiconductor circuit chip with the switching driver, while a lower power switching is also an N-channel FET, but is external to the driver chip. Either of the two power switching FETs may be configured to include a pilot FET cell, to facilitate current sensing for the controller.