Patents by Inventor Gregg Alan Bouchard

Gregg Alan Bouchard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11061724
    Abstract: Method and system embodying the method for programmable scheduling encompassing: enqueueing at least one command into one of a plurality of queues having a plurality of entries; determining a category of the command at the head entry of each of the plurality of queues; processing each determined non-job category command by a non-job command arbitrator; and processing each determined job category command by a job arbitrator and assignor, is disclosed.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: July 13, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Timothy Toshio Nakada, Jason Daniel Zebchuk, Gregg Alan Bouchard, Tejas Maheshbhai Bhatt, Hong Jik Kim, Ahmed Shahid, Mark Jon Kwong
  • Patent number: 11010318
    Abstract: Method and system embodying the method for a direct memory access between a data storage and a data processing device via one or more direct memory access units, comprising transferring data between the data storage and a first direct memory access engine of a respective one or more direct memory access units and providing the data for a second direct memory access engine of the respective one or more direct memory access units; and transferring the data provided by the first direct memory access engine by a second direct memory access engine to the data processing device via the second direct memory access engine is disclosed.
    Type: Grant
    Filed: May 14, 2016
    Date of Patent: May 18, 2021
    Assignee: CAVIUM INTERNATIONAL
    Inventors: Jason Daniel Zebchuk, Gregg Alan Bouchard, Tejas Maheshbhai Bhatt, Hong Jik Kim, Ahmed Shahid
  • Patent number: 10740256
    Abstract: A method utilizing a system encompassing a free pool buffer; a deadlock avoidance buffer; and a controller communicatively coupled to the free pool buffer and the deadlock avoidance buffer to reorder out-of-order responses to fetch requests into correct order by: receiving a fetch request on behalf of a consumer; allocating space first in the free pool buffer and when such space is not available then allocating space in a division associated with the consumer in the deadlock avoidance buffer. Issuing segment(s) of the fetch request including associated tag(s) to one of one or more memories; writing response data for each of the segment(s) to the allocated space in the free buffer or the deadlock avoidance buffer according to each of the associated tag(s); and transferring the response data to the consumer according to an entry in an ordering first-in, first-out buffer and an entry in a pending request array.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: August 11, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Kalyana Sundaram Venkataraman, Jason Daniel Zebchuk, Gregg Alan Bouchard, Tejas Maheshbhai Bhatt, Hong Jik Kim, Eric Marenger, Ahmed Shahid
  • Patent number: 10713089
    Abstract: Method and system embodying the method for load balancing of scheduled jobs among a plurality of engines encompassing determining a number of cluster credits for each of a plurality of clusters that comprise at least one engine capable of processing a scheduled job; determining a number of engine credits for each of the plurality of engines comprising each of the at least one engine in accordance with a number of jobs assigned to each of the plurality of engines; evaluating the determined number of cluster credits and the determined number of engine credits in accordance with a credit evaluation policy; and assigning the job to one of the plurality of engines in accordance with the evaluation, is disclosed.
    Type: Grant
    Filed: May 20, 2017
    Date of Patent: July 14, 2020
    Assignee: CAVIUM INTERNATIONAL
    Inventors: Timothy Toshio Nakada, Jason Daniel Zebchuk, Gregg Alan Bouchard, Tejas Maheshbhai Bhatt, Hong Jik Kim, Ahmed Shahid, Mark Jon Kwong
  • Patent number: 10635497
    Abstract: A method and a system embodying the method for job pre-scheduling in a processing system comprising distributed job management, encompassing: determining a maximum amount of pre-schedulable jobs for each of a plurality of engines; setting for each of the plurality of engines a threshold less than or equal to the maximum amount; pre-scheduling by a scheduler an amount of jobs less than or equal to the threshold to at least one of a plurality of job managers; determining at the at least one of the plurality of job managers managing one of the plurality of engines one of a plurality of data processing devices in order for each pre-scheduled job; and assigning the job to the determined data processing device.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: April 28, 2020
    Assignee: Cavium, LLC
    Inventors: Kalyana Sundaram Venkataraman, Tejas Maheshbhai Bhatt, Hong Jik Kim, Eric Marenger, Ahmed Shahid, Jason Daniel Zebchuk, Gregg Alan Bouchard
  • Publication number: 20180349185
    Abstract: Method and system embodying the method for programmable scheduling encompassing: enqueueing at least one command into one of a plurality of queues having a plurality of entries; determining a category of the command at the head entry of each of the plurality of queues; processing each determined non-job category command by a non-job command arbitrator; and processing each determined job category command by a job arbitrator and assignor, is disclosed.
    Type: Application
    Filed: June 5, 2017
    Publication date: December 6, 2018
    Applicant: Cavium, Inc.
    Inventors: Timothy Toshio Nakada, Jason Daniel Zebchuk, Gregg Alan Bouchard, Tejas Maheshbhai Bhatt, Hong Jik Kim, Ahmed Shahid, Mark Jon Kwong
  • Publication number: 20180341602
    Abstract: A method utilizing a system encompassing a free pool buffer; a deadlock avoidance buffer; and a controller communicatively coupled to the free pool buffer and the deadlock avoidance buffer to reorder out-of-order responses to fetch requests into correct order by: receiving a fetch request on behalf of a consumer; allocating space first in the free pool buffer and when such space is not available then allocating space in a division associated with the consumer in the deadlock avoidance buffer. Issuing segment(s) of the fetch request including associated tag(s) to one of one or more memories; writing response data for each of the segment(s) to the allocated space in the free buffer or the deadlock avoidance buffer according to each of the associated tag(s); and transferring the response data to the consumer according to an entry in an ordering first-in, first-out buffer and an entry in a pending request array.
    Type: Application
    Filed: May 23, 2017
    Publication date: November 29, 2018
    Applicant: Cavium, Inc.
    Inventors: Kalyana Sundaram Venkataraman, Jason Daniel Zebchuk, Gregg Alan Bouchard, Tejas Maheshbhai Bhatt, Hong Jik Kim, Eric Marenger, Ahmed Shahid
  • Publication number: 20180336063
    Abstract: Method and system embodying the method for load balancing of scheduled jobs among a plurality of engines encompassing determining a number of cluster credits for each of a plurality of clusters that comprise at least one engine capable of processing a scheduled job; determining a number of engine credits for each of the plurality of engines comprising each of the at least one engine in accordance with a number of jobs assigned to each of the plurality of engines; evaluating the determined number of cluster credits and the determined number of engine credits in accordance with a credit evaluation policy; and assigning the job to one of the plurality of engines in accordance with the evaluation, is disclosed.
    Type: Application
    Filed: May 20, 2017
    Publication date: November 22, 2018
    Applicant: Cavium, Inc.
    Inventors: Timothy Toshio Nakada, Jason Daniel Zebchuk, Gregg Alan Bouchard, Tejas Maheshbhai Bhatt, Hong Jik Kim, Ahmed Shahid, Mark Jon Kwong
  • Publication number: 20180321983
    Abstract: A method and a system embodying the method for job pre-scheduling in a processing system comprising distributed job management, encompassing: determining a maximum amount of pre-schedulable jobs for each of a plurality of engines; setting for each of the plurality of engines a threshold less than or equal to the maximum amount; pre-scheduling by a scheduler an amount of jobs less than or equal to the threshold to at least one of a plurality of job managers; determining at the at least one of the plurality of job managers managing one of the plurality of engines one of a plurality of data processing devices in order for each pre-scheduled job; and assigning the job to the determined data processing device.
    Type: Application
    Filed: May 5, 2017
    Publication date: November 8, 2018
    Applicant: Cavium, Inc.
    Inventors: Kalyana Sundaram Venkataraman, Tejas Maheshbhai Bhatt, Hong Jik Kim, Eric Marenger, Ahmed Shahid, Jason Daniel Zebchuk, Gregg Alan Bouchard
  • Publication number: 20170329731
    Abstract: Method and system embodying the method for a direct memory access between a data storage and a data processing device via one or more direct memory access units, comprising transferring data between the data storage and a first direct memory access engine of a respective one or more direct memory access units and providing the data for a second direct memory access engine of the respective one or more direct memory access units; and transferring the data provided by the first direct memory access engine by a second direct memory access engine to the data processing device via the second direct memory access engine is disclosed.
    Type: Application
    Filed: May 14, 2016
    Publication date: November 16, 2017
    Applicant: Cavium, Inc.
    Inventors: Jason Daniel Zebchuk, Gregg Alan Bouchard, Tejas Maheshbhai Bhatt, Hong Jik Kim, Ahmed Shahid
  • Publication number: 20170301382
    Abstract: Method and system embodying the method for a general address transformation for an access to a shared memory comprising at least one tile and each tile comprising at least one memory bank, comprising selecting a mode of a general address transformation; providing a general address comprising a plurality of bits by at least one of a plurality of devices; and transforming the general address onto a transformed address according to the selected mode; wherein in a first selected mode the transforming comprises determining each of a plurality of bits of a transformed address as an exclusive or of at least two bits of the plurality of bits of the general address provided that the shared memory comprises a plurality of tiles, and/or each tile comprises a plurality of banks is disclosed.
    Type: Application
    Filed: April 14, 2016
    Publication date: October 19, 2017
    Applicant: Cavium, Inc.
    Inventors: Jason Daniel Zebchuk, Gregg Alan Bouchard, David Glen Roe