Patents by Inventor Gregg B. Lesartre

Gregg B. Lesartre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11349771
    Abstract: One embodiment of the present invention provides a switch. During operation, the switch maintains a first counter to indicate a first number of packets in a queue of the switch. The switch then determines whether a clock of the switch has reached a threshold value. If the clock reaches the threshold value, the switch starts maintaining a second counter to indicate a second number of packets in the queue that have been received after the clock has reached the threshold value. The switch continues to decrement the first counter in response to a packet leaving the queue until the first counter reaches a value of zero. When the clock reaches a maximum value supported by the clock, the switch drops a third number of packets from the queue indicated by the first counter.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: May 31, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Jason Jung, Norell Estella Menhusen, Christopher Michael Brueggen
  • Publication number: 20220138128
    Abstract: A method comprises receiving a message comprising an identifier for an address template, using the identifier to select the address template from a set of address templates, determining a set of memory addresses for a corresponding set of memory operations using the address template, and executing the memory operations.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 5, 2022
    Inventors: Gregg B. Lesartre, Darel Neal Emmot
  • Patent number: 11221967
    Abstract: A system and method for addressing split modes of persistent memory are described herein. The system includes a non-volatile memory comprising regions of memory, each region comprising a range of memory address spaces. The system also includes a memory controller (MC) to control access to the non-volatile memory. The system further includes a device to track a mode of each region of memory and to define the mode of each region of memory. The mode is a functional use model.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: January 11, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Blaine D. Gaither, Dale C. Morris, Carey Huscroft, Russ W. Herrell
  • Patent number: 11197152
    Abstract: A component group table in a receiving node of a computer network stores access permission information for enabling the receiving node to validate an access request issued by a requesting node. An incoming access request at a receiving node includes a subnet ID/component ID (“SID/CID”) tuple. The receiving node selectively computes a component group table address for the requesting node according to an address mapping function determined by the value of at least one predetermined bit within the SID/CID tuple of the incoming access request. Using at least one bit in the SID/CID tuple enables the establishment of at least two address mapping regions in the component group table, such as separate regions for storage nodes and compute nodes in the network.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: December 7, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Gary B. Gostin, Nicholas McDonald
  • Publication number: 20210344610
    Abstract: One embodiment of the present invention provides a switch. During operation, the switch maintains a first counter to indicate a first number of packets in a queue of the switch. The switch then determines whether a clock of the switch has reached a threshold value. If the clock reaches the threshold value, the switch starts maintaining a second counter to indicate a second number of packets in the queue that have been received after the clock has reached the threshold value. The switch continues to decrement the first counter in response to a packet leaving the queue until the first counter reaches a value of zero. When the clock reaches a maximum value supported by the clock, the switch drops a third number of packets from the queue indicated by the first counter.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 4, 2021
    Inventors: Gregg B. Lesartre, Jason Jung, Norell Estella Menhusen, Christopher Michael Brueggen
  • Publication number: 20210342266
    Abstract: One embodiment can provide an apparatus. The apparatus can include a persistent flush (PF) cache and a PF-tracking logic coupled to the PF cache. The PF-tracking logic is to: in response to receiving, from a media controller, an acknowledgment to a write request, determine whether the PF cache includes an entry corresponding to the media controller; in response to the PF cache not including the entry corresponding to the media controller, allocate an entry in the PF cache for the media controller; in response to receiving a persistence checkpoint, identify a media controller from a plurality of media controllers based on entries stored in the PF cache; issue a persistent flush request to the identified media controller to persist write requests received by the identified media controller; and remove an entry corresponding to the identified media controller from the PF cache subsequent to issuing the persistent flush request.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 4, 2021
    Inventors: Derek A. Sherlock, Gregg B. Lesartre
  • Patent number: 11126372
    Abstract: A computing system is disclosed herein. The computing system includes a computing node and a remote memory node coupled to the computing node via a system fabric. The computing node includes a plurality of processors and a master memory controller. The master memory controller is external to the plurality of processors. The master memory controller routes requests corresponding to requests from the plurality of processors across the system fabric to the remote memory node and returns a response.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: September 21, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Russ W. Herrell, Gary Gostin, Gregg B Lesartre, Dale C. Morris
  • Patent number: 11119780
    Abstract: A device including a processor configured to access data to execute multiple instructions and a first cache coupled to the processor, are provided. The first cache is configured to hold a first data fetched from a memory by a first instruction that has been retired. The device also includes a side cache coupled to the first cache and to the processor, the side cache configured to hold a second data fetched from the memory by a second instruction, wherein the second instruction has not been retired from the processor. And the device includes a cache management unit configured to move the second data from the side cache to the first cache when the second instruction is retired, the cache management unit further configured to discard the second data when it is determined that the second instruction is abandoned.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: September 14, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Gregg B. Lesartre
  • Patent number: 11086797
    Abstract: A method for restricting write access to a non-volatile memory. The method includes receiving a request to write to a protected location in the non-volatile memory and determining whether the protected location is in a write-protected state. If the protected location is not in a write-protected state, the method includes writing data indicated by the request to the protected location. If the protected location is in a write-protected state, the method includes rejecting the request. The protected location stores a validation key to validate the contents of another portion of the non-volatile memory.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: August 10, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Joseph E. Foster, David Plaquin, James M. Mann
  • Publication number: 20210185516
    Abstract: A component group table in a receiving node of a computer network stores access permission information for enabling the receiving node to validate an access request issued by a requesting node. An incoming access request at a receiving node includes a subnet ID/component ID (“SID/CID”) tuple. The receiving node selectively computes a component group table address for the requesting node according to an address mapping function determined by the value of at least one predetermined bit within the SID/CID tuple of the incoming access request. Using at least one bit in the SID/CID tuple enables the establishment of at least two address mapping regions in the component group table, such as separate regions for storage nodes and compute nodes in the network.
    Type: Application
    Filed: December 12, 2019
    Publication date: June 17, 2021
    Inventors: Gregg B. Lesartre, Gary B. Gostin, Nicholas McDonald
  • Publication number: 20210167038
    Abstract: According to an example, a dual in-line memory module (DIMM) may include a high density package substrate including a plurality of connectors for communicatively interconnecting the DIMM to a system.
    Type: Application
    Filed: February 16, 2021
    Publication date: June 3, 2021
    Inventors: Gregg B. Lesartre, Jason H. Culler, Martin Foltin, William S. Jaffe
  • Patent number: 11016683
    Abstract: According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: May 25, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Harvey Ray, Gary Gostin, Derek Alan Sherlock, Gregg B. Lesartre
  • Patent number: 10983865
    Abstract: In various examples, a device comprises a memory. The memory comprises a plurality of dies and logic. The logic may: determine a tolerable bit error rate (BER) of the memory based on whether one of the plurality of dies has failed, and adjust a parameter of the memory based on the tolerable BER.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: April 20, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Martin Foltin
  • Publication number: 20210112015
    Abstract: Candidates for selection in a weighted arbitration system are assigned priority weights and random weights. The winning candidate is determined using a tree of selectors such as a comparators. At each stage of the tree, the candidate having the greatest priority weight is selected to pass to the next stage. If multiple candidates are tied for the greatest priority weight, the candidate having the greatest random weight is selected to pass to the next stage.
    Type: Application
    Filed: October 15, 2020
    Publication date: April 15, 2021
    Inventors: Gregg B. Lesartre, Darel Neal Emmot, James D. Gibson
  • Patent number: 10972394
    Abstract: Example implementations relate to congestion management across a network fabric. An example implementation includes setting an uncongested sequence length threshold to a first value. A completed transaction received count may also be set to an initial value. The completed transaction received count may be incremented in response to a completion of a transaction request. In response to a detected congestion event, the injection rate may be decreased. A second value for the uncongested sequence length threshold may be determined from the CTR count, and the uncongested sequence length threshold may be set to the second value. Furthermore, in response to the CTR count being greater than or equal to the uncongested sequence length threshold, the injection rate may be increased.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 6, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Derek Alan Sherlock, Nicholas George McDonald
  • Patent number: 10922178
    Abstract: A system includes byte-addressable non-volatile memory (NVM) modules. The system includes media controllers communicatively connected to one another over a memory semantic fabric. Each media controller is responsible for a corresponding NVM module to which the media controller is attached. The media controllers cooperatively provide redundant array of independent disks (RAID) functionality at a granularity at which the NVM modules are byte-addressable without employing a master RAID controller.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: February 16, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Russ W. Herrell, Chris Michael Brueggen
  • Publication number: 20200356497
    Abstract: A communications device that includes a requester and a responder may support multiple transaction classes, including an ordered transaction class, while maintaining a bifurcated requester/responder architecture. Before a responder has a non-posted transaction response to transmit on an interconnect, it receives an indication from the requester that there is not a pending posted transaction on the interconnect.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 12, 2020
    Inventors: Gregg B. Lesartre, Derek Alan Sherlock
  • Patent number: 10824465
    Abstract: A method may include receiving a first transaction request. The method may further include transmitting a retry response to the transaction request, which includes a first epoch identifier associated with a current epoch. The method may further include receiving a second transaction request, which includes a second epoch identifier associated with a previous epoch. The second transaction request may be fulfilled using a transaction resource reserved for the previous epoch.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: November 3, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Derek Alan Sherlock
  • Patent number: 10817361
    Abstract: A technique includes receiving an alert indicator in a distributed computer system that includes a plurality of computing nodes coupled together by cluster interconnection fabric. The alert indicator indicates detection of a fault in a first computing node of the plurality of computing nodes. The technique indicates regulating communication between the first computing node and at least one of the other computing nodes in response to the alert indicator to contain error propagation due to the fault within the first computing node.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: October 27, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B Lesartre, Dale C Morris, Russ W Herrell, Blaine D Gaither
  • Patent number: 10802936
    Abstract: In one example a system includes a memory, and at least one memory controller to: detect a failed first memory location of the memory, remap the failed first location of the memory to a spare second location of the memory based on a pointer stored at the failed first memory location, and wear-level the memory. To wear-level the memory, the memory controller may copy data from the spare second location of the memory to a third location of the memory, and keep the pointer in the failed first memory location.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: October 13, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B Lesartre, Ryan Akkerman, Joseph F Orth