Patents by Inventor Gregory B. Wiedenman

Gregory B. Wiedenman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7797472
    Abstract: A multiprocessor system in which a defer phase response method is utilized that allows for a deferring agent to interrupt the normal flow of bus transactions once it gains control of system interface bus. The deferring agent is allowed to look ahead to determine if a continuous stream of defer phase cycles are pending transfer. If pending, the deferring agent will not release control of the bus until the pending defer phase cycles have been depleted. The look ahead feature allows expedited return of higher priority defer data, while minimizing bus dead cycles caused by interleaving defer phase cycles with normal bus traffic.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: September 14, 2010
    Assignee: Unisys Corporation
    Inventors: Gregory B. Wiedenman, Nathan A. Eckel, Kelvin S. Vartti
  • Patent number: 7739451
    Abstract: A method and apparatus is presented allowing multiple data pointers or addresses to be transferred without acknowledgment to Memory Controller (506) and Memory Controller (510) of Data Controller (500). Data is then transferred in response to the data pointers from BUFFER (512) and Buffer (514) and may be stalled during the transfer in favor of a second data transfer. Once the second data transfer finishes, the first data transfer may be completed.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: June 15, 2010
    Assignee: Unisys Corporation
    Inventors: Gregory B. Wiedenman, Nathan A. Eckel, Joel B. Artmann
  • Publication number: 20090172225
    Abstract: A multiprocessor system in which a defer phase response method is utilized that allows for a deferring agent to interrupt the normal flow of bus transactions once it gains control of system interface bus. The deferring agent is allowed to look ahead to determine if a continuous stream of defer phase cycles are pending transfer. If pending, the deferring agent will not release control of the bus until the pending defer phase cycles have been depleted. The look ahead feature allows expedited return of higher priority defer data, while minimizing bus dead cycles caused by interleaving defer phase cycles with normal bus traffic.
    Type: Application
    Filed: August 25, 2004
    Publication date: July 2, 2009
    Inventors: Gregory B. Wiedenman, Nathan A. Eckel, Kelvin S. Vartti
  • Patent number: 7421545
    Abstract: Bus address, function and system information in relation to bus requests are maintained in a centralized location (702). Parallel access to the centralized data is facilitated through the use of pointers to the centralized location. Bus transaction operations needing access to the centralized data are simultaneously connected to the data through the use of the pointer control (610), rather than requiring the data to be sequentially transmitted to the bus transaction operations as required.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: September 2, 2008
    Assignee: Unisys Corporation
    Inventors: Gregory B. Wiedenman, Nathan A. Eckel
  • Patent number: 7051131
    Abstract: A method and apparatus to facilitate a history trace of system bus activity in a Symmetric Multi-Processor (SMP) environment. A dynamic scan capability is provided to User (516) via Computer (504) that allows dynamic configuration of History Control Register (518), thus providing a maskable history stack of system bus activity to be obtained from History Memory (508) for subsequent analysis.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: May 23, 2006
    Assignee: Unisys Corporation
    Inventors: Gregory B. Wiedenman, Nathan A. Eckel, Mary C. Roskowiak
  • Patent number: 7003628
    Abstract: A data transfer system uses a data buffer and individual control of each storage location within the data buffer for improved control of data block transfers. The storage locations are assigned deallocate, active, or valid assignment bands to enable transfer control of the data blocks within the system. The deallocated storage locations are returned to an allocation pool for use as a future resource, where the active and valid assignment bands remain unavailable until deallocated. Error checking and depth control prohibit consecutive allocation or deallocation assignments as well as overflow.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: February 21, 2006
    Assignee: Unisys Corporation
    Inventors: Gregory B. Wiedenman, Nathan A.. Eckel, Raymond G. Ryan
  • Patent number: 6996645
    Abstract: Coded requests are received from Memory Port Interfaces (608 and 612) and stored into Outgoing Queue (604). Coded requests are also received from Transaction Pipeline (610), some of which may be linked requests. In response to each linked request stored in Outgoing Queue (604), multiple bus requests are generated by Outgoing Queue (604) and assembled by Assembler (602) and placed onto Bus Interface (620).
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: February 7, 2006
    Assignee: Unisys Corporation
    Inventors: Gregory B. Wiedenman, Nathan A. Eckel
  • Patent number: 6012148
    Abstract: An error detection and recovery apparatus for monitoring, and recovering from, errors in a system having one or more logic units. An error detector detects errors in the logic units, and provides error signals in response. A first error processor receives selected error signals, and performs system recovery according to the particular error signals present. A second error processor receives other selected error signals, and performs error recovery of the logic unit only, without affecting the rest of the system. The second error processor performs error recovery through real-time execution of error recovery routines at the logic unit. A selector is provided to determine which of the error signals are provided to the first and second error processors. A memory stack having multiple memory locations is also provided to store bus information captured from a bus, which can be used by the second error processor in its error recovery.
    Type: Grant
    Filed: January 29, 1997
    Date of Patent: January 4, 2000
    Assignee: Unisys Corporation
    Inventors: Paul A. Laberge, Gregory B. Wiedenman
  • Patent number: 5671369
    Abstract: A circuit employing two delayed bus clock signals and timer logic to minimize the dead bus time occurring between consecutive bus drivers and providing additional protection against multiple, simultaneous bus drivers for a communications bus in a computer system. Skewed enable and disable clock signals based on an original bus clock feed combinational logic to set a transceiver enable line when control of the bus is granted for bus transfers. Bus transfers remain enabled, through use of a feedback path, as long as a bus grant signal is active. When the last cycle of the bus transfer occurs, or a bus transfer error occurs, the transceiver enable line goes inactive, thereby allowing other components coupled to the bus to gain control. Test mode and bus transfer status lines provide further mechanisms for controlling bus transfer operation.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: September 23, 1997
    Assignee: Unisys Corporation
    Inventors: Paul A. LaBerge, Gregory B. Wiedenman, Donald E. Harding
  • Patent number: 5664089
    Abstract: A power loss detection and recovery circuit for providing continued memory operations upon loss of a supply voltage. Multiple independent power domains, each of which provides an electrically isolated supply voltage, are used to provide power to redundant memory circuitry. A loss of voltage or a degenerative voltage within a power domain is detected, and circuitry residing on a different operational power domain provides recovery operations to allow continued memory activity within that operational power domain. The memories residing in an adjacent pair of power domains redundant, and are therefore written to and read from simultaneously, and circuitry within an operational power domain will prevent further reading of data from the memory residing in a failed power domain, and will also prevent further writing of data to the memory residing in the failed power domain upon recognition of a failed supply voltage within a power domain.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: September 2, 1997
    Assignee: Unisys Corporation
    Inventors: Larry L. Byers, David J. Tanglin, Paul A. LaBerge, Gregory B. Wiedenman
  • Patent number: 5581482
    Abstract: An apparatus for monitoring the performance of a computer system. A number of performance monitoring hardware elements may be placed throughout a computer system to simultaneously monitor the performance of a number of distinct components within the computer system. An advantage of the present invention over a software based approach is that the present invention allows any node within the computer system to be monitored. In addition, the present invention does not run on the systems CPU and therefore the performance monitoring function does not decrease system performance while operating. Finally, because the present invention does not run on the system's CPU, the results of the performance monitoring function may be more accurate than a software base approach.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: December 3, 1996
    Assignee: Unisys Corporation
    Inventors: Gregory B. Wiedenman, Randy L. DeGarmo
  • Patent number: 5495589
    Abstract: A computer architecture for providing enhanced reliability by coupling a plurality of commonly shared busses called streets with a plurality of smart switching elements called HUBs. The streets are bi-directional busses for transferring data between HUB elements. The HUB elements are capable of directing data across the street structures to the desired destination. The HUB elements have a built in priority scheme for allowing high priority data to be transferred before low priority data. The either increase or decrease the number of HUB elements and streets can be.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: February 27, 1996
    Assignee: Unisys Corporation
    Inventors: Donald W. Mackenthun, Larry L. Byers, Gregory B. Wiedenman, Ferris T. Price, deceased
  • Patent number: 5422915
    Abstract: A fault tolerant multiple phase clock distribution system for providing synchronized clock signals to multiple circuit loads. Multiple electrically isolated power domains are powered by redundant AC and DC power sourcing circuits to ensure continued operation upon partial failure of the AC or DC power sourcing circuits. Multiple oscillators from the multiple power domains are synchronized to produce a group of simultaneously synchronized clock signals. Multiple synchronized clock signals from this group are then selected by selection circuitry and selection control circuitry, and are distributed to multiple circuit loads requiring simultaneous synchronization. The oscillator circuitry, synchronization circuitry, selection circuitry, and distribution circuitry is all provided in redundant form, so that the partial failure of any of the circuitry will not result in a system stop.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: June 6, 1995
    Assignee: Unisys Corporation
    Inventors: Larry L. Byers, Thomas T. Kubista, Gregory B. Wiedenman
  • Patent number: 5381416
    Abstract: A skew fault detection system for detecting clock skew between two clock phases utilizes a plurality of skew fault detection circuits each of which employs two D-type flip-flops. The clock terminals of both of these flip-flops are connected to one of the clock phases, and one of the clock phases is coupled to a delay circuit on the D input terminal of one of the flip-flops. The delay circuit is adjustable to correspond to the clock pulse delay that is inherent in the circuit that is being monitored to control the maximum amount of clock skew that is allowable before this flip-flop will set. If the clock skew exceeds this allowable time, a skew fault occurs and the flip-flop will set. The circuit compares the initiation of one clock phase against the initiation of the other clock phase and to determine when the initiation of one clock phase occurs earlier than the initiation of the other clock pulse by a time duration that exceeds a predetermined allowable skew amount of time.
    Type: Grant
    Filed: November 8, 1993
    Date of Patent: January 10, 1995
    Assignee: Unisys Corporation
    Inventors: Kelvin S. Vartti, Gregory B. Wiedenman
  • Patent number: 4646076
    Abstract: A method and apparatus for performing high speed graphics fill is provided. Any closed line geometric shape or polygon that can be defined by pixel position is stored in memory. The memory pixel positions are stored in address locations corresponding to row and column positions. A first sequential examination of the data is made in reverse raster scan order to make a preliminary determination of the pixel positions inside the closed polygon. A second sequential examination of the data is made in forward or regular raster scan order and a final determination is made whether the pixel positions are inside the polygon and shall be filled. The final determination of pixel positions to be filled is stored shortly before the graphics fill operation is performed so that the fill operation is performed in raster scan time at high speed.
    Type: Grant
    Filed: April 27, 1983
    Date of Patent: February 24, 1987
    Assignee: Sperry Corporation
    Inventors: Gregory B. Wiedenman, Kenneth S. Morley, Gary H. Frederickson, Jeffrey L. Williams
  • Patent number: 4595996
    Abstract: A video display control circuit, for an intelligent terminal, includes a large cost efficient Random-Access Memory (RAM). A portion of the RAM memory is utilized as a high speed character generator instead of employing a dedicated Read Only Memory (ROM). Novel timing and memory control circuits are provided which permit characters to be generated witout any delay or change of real character timing. The characters in RAM may be modified or changed which is not possible with dedicated Read Only Memories.
    Type: Grant
    Filed: April 25, 1983
    Date of Patent: June 17, 1986
    Assignee: Sperry Corporation
    Inventors: Kenneth S. Morley, Gregory B. Wiedenman, James K. White
  • Patent number: 4334287
    Abstract: A buffer memory arrangement for use in conjunction with a controller and a plurality of peripheral units and/or subsystems of a data processing system. The arrangement includes a dynamic RAM buffer memory for receiving and storing information from the peripheral units or subsystems and for supplying stored information to such units, an address pointer memory for storing buffer memory addresses identifying locations in buffer memory from which information is to be read or into which information is to be stored, and an encoder responsive to a request signal from a peripheral unit or subsystem for supplying an identity signal to the address pointer memory, which signal identifies the requesting peripheral unit or subsystem and specifies location in the address pointer memory containing buffer memory addresses which are to be applied to the buffer memory.
    Type: Grant
    Filed: April 12, 1979
    Date of Patent: June 8, 1982
    Assignee: Sperry Rand Corporation
    Inventors: Gregory B. Wiedenman, Phillip W. Marsh
  • Patent number: 4326291
    Abstract: In a throughput error detection system, a redundant logic unit is provided along with a required logic unit for simultaneous operation therewith. The required logic unit and redundant logic unit both produce output data which, it is desired, will be the same. The output data from the required logic unit is supplied to a data bus and the output data of the redundant logic unit is supplied to a parity check digit generator. From the data received from the redundant logic unit, the parity check digit generator generates a parity check digit which is applied to the data bus along wih the data from the required logic unit. A parity checking circuit receives the data and the parity check digit from the data bus and a calculation is made by the circuit to determine if parity is correct. If parity is not correct, the checking circuit produces an alarm signal to alert a user.
    Type: Grant
    Filed: April 11, 1979
    Date of Patent: April 20, 1982
    Assignee: Sperry Rand Corporation
    Inventors: Phillip W. Marsh, Gregory B. Wiedenman
  • Patent number: 4237535
    Abstract: Peripheral devices of a microprocessor controlled system initiate service request signals which are sent to a system controller over a single dedicated request line. Such request signals are accepted by the system controller on a priority basis, with only one service request signal being honored at any given time. Once honored, the system controller addresses the peripheral device and accepts a vector request word therefrom. The vector request word is then used by the system controller to generate an index signal to select a microaddress of the microroutine to be used to service a peripheral device's request.
    Type: Grant
    Filed: April 11, 1979
    Date of Patent: December 2, 1980
    Assignee: Sperry Rand Corporation
    Inventor: Gregory B. Wiedenman