Patents by Inventor Gregory J. Armstrong

Gregory J. Armstrong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5571736
    Abstract: An EPROM disclosed in this specification includes a unique floating gate memory cell which may be charged using a reduced voltage level. The memory cells are fabricated using a mask to define the buried source, drain, and field oxide regions of the memory cell. After removal of the mask, field oxide regions are formed and a floating gate is fabricated which extends beyond the boundaries of the channel region for the floating gate field effect transistor memory cell. This extended floating gate provides additional capacitive coupling between the gate/word line and the floating gate while maintaining the same capacitive coupling between the floating gate and the channel of the floating gate field effect transistor memory cell. One embodiment discloses a silicide which is applied to the buried source and drain regions. The silicide is fabricated by forming a slot through the field oxide, forming a silicide on the diffused regions, refilling the slot with an oxide, and planarizing the resulting structure.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 5, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: James L. Paterson, Gregory J. Armstrong
  • Patent number: 5374580
    Abstract: A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar in structure to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.
    Type: Grant
    Filed: September 30, 1993
    Date of Patent: December 20, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: David A. Baglee, Robert R. Doering, Gregory J. Armstrong
  • Patent number: 5170234
    Abstract: A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar in structure to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A word line forms the gate of the access transistor at a hole in the polysilicon field plate.
    Type: Grant
    Filed: August 27, 1991
    Date of Patent: December 8, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: David A. Baglee, Robert R. Doering, Gregory J. Armstrong
  • Patent number: 4696092
    Abstract: A dynamic read/write memory or the like is made by a twin-well CMOS process that employs field-plate isolation rather than thick field oxide, with no separate channel stop implant. The field plate is grounded over P well areas, and connected to the positive supply over the N wells. One-transistor memory cells are of metal-gate construction with N+ drain regions buried beneath oxide, and other transistors are constructed with silicided, implanted, source/drain regions, self-aligned to the metal gates, employing sidewall oxide spacers to provide lightly-doped drains.
    Type: Grant
    Filed: December 31, 1985
    Date of Patent: September 29, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Robert R. Doering, Gregory J. Armstrong
  • Patent number: 4677739
    Abstract: A semiconductor device such as a dynamic read/write memory or the like is made by a twin-well CMOS process that employs a minimum number of photomasks. Field oxide isolation areas are formed in nitride-framed recesses so a relatively plane surface is provided, and a minimum of encroachment occurs. Both P-channel and N-channel transistors are constructed with silicided, ion-implanted, source/drain regions, self-aligned to the gates, employing an implant after sidewall oxide is in place, providing lightly-doped drains. The threshold voltages of the P-channel and N-channel transistors are established by the tank implants rather than by separate ion-implant steps for threshold adjust.
    Type: Grant
    Filed: November 29, 1984
    Date of Patent: July 7, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Robert R. Doering, Michael P. Duane, Gregory J. Armstrong
  • Patent number: 4561170
    Abstract: A dynamic read/write memory or the like is made by a twin-well CMOS process that employs field-plate isolation rather than thick field oxide, with no separate channel stop implant. The field plate is grounded over P well areas, and connected to the positive supply over the N wells. One-transistor memory cells are of metal-gate construction with N+ drain regions buried beneath oxide, and other transistors are constructed with silicided, implanted, source/drain regions, self-aligned to the metal gates, employing sidewall oxide spacers to provide lightly-doped drains.
    Type: Grant
    Filed: July 2, 1984
    Date of Patent: December 31, 1985
    Assignee: Texas Instruments Incorporated
    Inventors: Robert R. Doering, Gregory J. Armstrong