Abstract: The present techniques relate to various aspects of forming and filling high-aspect ratio trench structures (e.g., trench structures having an aspect ratio of 20 or greater, including aspect ratios in the range of 20:1 up to and including 50:1 or greater) combined with trench opening widths ranging from 0.5 micron to 50 microns. By way of example, patterned substrate described herein includes a substrate, a mask layer deposited on the substrate, and a photoresist layer deposited on the mask layer. The photoresist layer is patterned to form a pattern and the mask layer is etched through the pattern to expose the substrate. The substrate is etched through the pattern to form a structure comprising a plurality of trenches having vertical sidewall. The photoresist layer remains on the mask layer during etching of the substrate.

Abstract: The present techniques relate to various aspects of forming and filling high-aspect ratio trench structures (e.g., trench structures having an aspect ratio of 20 or greater, including aspect ratios in the range of 20:1 up to and including 50:1 or greater) combined with trench opening widths ranging from 0.5 micron to 50 microns. In one implementation a method to fabricate high-aspect ratio trenches in silicon is provided using a patterned photoresist on evaporated aluminum. In accordance with this approach, a high-aspect ratio trench can be formed having vertical side walls and defect-free trench bottoms. In some instances it may be desirable to fill such high-aspect ratio trench structures with a metal or other substrate to provide certain functionality associated with the fill material. Further processes and structures are related in which such trench structures are filled using a mixture of high-Z nano-particles within an epoxy resin matrix.

Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.

Abstract: A method for sputtering an aluminum layer on a surface of a semiconductor device is presented. The method includes three sputtering steps for depositing the aluminum layer, where each sputtering step includes at least one sputtering parameter that is different from a corresponding sputtering parameter of another sputtering step. The surface of the semiconductor device includes a dielectric layer having a plurality of openings formed through the dielectric layer.

Abstract: A method for sputtering an aluminum layer on a surface of a semiconductor device is presented. The method includes three sputtering steps for depositing the aluminum layer, where each sputtering step includes at least one sputtering parameter that is different from a corresponding sputtering parameter of another sputtering step. The surface of the semiconductor device includes a dielectric layer having a plurality of openings formed through the dielectric layer.

Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.

Abstract: The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 ?m.

Abstract: The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 ?m.