Patents by Inventor Gregory Lee Christison
Gregory Lee Christison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8983012Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.Type: GrantFiled: January 25, 2012Date of Patent: March 17, 2015Assignee: Texas Instruments IncorporatedInventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Gregory Lee Christison
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Publication number: 20120121051Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.Type: ApplicationFiled: January 25, 2012Publication date: May 17, 2012Applicant: Texas Instruments IncorporatedInventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Gregory Lee Christison
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Patent number: 8130889Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.Type: GrantFiled: April 4, 2005Date of Patent: March 6, 2012Assignee: Texas Instruments IncorporatedInventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Gregory Lee Christison
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Patent number: 7269175Abstract: The present invention provides an apparatus, system and method for transmitting asynchronous transfer mode (ATM) data cells on an ATM adaptation layer (AAL) configured connection within an ATM system comprising a digital signal processor (DSP) sub-system (160) and a host processor (190). The transmitter interfaces directly with the DSP sub-system (160) (which converts the digitized voice samples into voice signals) and the host processor (190) (which performs AAL2 signaling and layer management functions). The transmitter is configured to interleave AAL2 voice packets from the DSP sub-system (160) and signaling and management packets from the host processor (190) on an ATM connection. Data is fetched by DMA(s) (415). A channel look-up table uses the DSP assigned voice channel as an index into the table to map a voice channel to the ATM connection.Type: GrantFiled: April 6, 2001Date of Patent: September 11, 2007Assignee: Texas Instruments IncorporatedInventors: Magnus Karlsson, Gregory Lee Christison, Norayda Humphrey
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Patent number: 7215670Abstract: A Universal Serial Bus (USB) modem (14) in which reassembly and segmentation operations are performed outside of the host computer (12) is disclosed. A USB interface device (30) is coupled to a digital signal processor (DSP) (32) in the modem (14), and contains a shared memory (44) in which bulk endpoints (51) are established, at which received ATM cell payload data may be stored. An ATM receive controller (134) is provided in the USB interface device (30), which receives each ATM cell from the DSP (32) and interrogates the ATM cell header to determine which, if any, virtual connection the cell corresponds. The ATM receive controller (134) then forwards the payload portion of the ATM cell, but not the ATM cell header, to the endpoint (51) corresponding to the virtual connection to which the ATM cell is directed. The disclosed ATM receive controller (134) also includes logic (64) for calculating a cyclic redundancy check value over the payload portion of the ATM cells that make up an ATM packet.Type: GrantFiled: February 18, 2000Date of Patent: May 8, 2007Assignee: Texas Instruments IncorporatedInventors: Magnus G. Karlsson, Norayda N. Humphrey, Gregory Lee Christison
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Patent number: 6990108Abstract: The present invention provides a unitary mechanism for high speed end-to-end telecommunication traffic using an Asynchronous Transfer Mode (ATM) architecture for convergence of video, data and voice in an SOHO application using a DSL router. An ATM module (101) for convergence of the telecommunications traffic includes an ATM processor (120) configured to perform QoS, OAM processing and switching in an ATM system. Function modules (102,104,105) and data ports (106,108) are configurable to transceive data, voice and video traffic in which the traffic is packetized in ATM data cells.Type: GrantFiled: April 6, 2001Date of Patent: January 24, 2006Assignee: Texas Instruments IncorporatedInventors: Magnus Karlsson, Gregory Lee Christison, Norayda Humphrey
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Patent number: 6961340Abstract: The present invention provides an apparatus, system and method for receiving asynchronous transfer mode (ATM) data cells on an ATM adaptation layer (AAL) configured connection within an ATM system comprising a digital signal processor (DSP) sub-system (412) and a host processor (414). The receiver interfaces directly with the DSP sub-system (412) (which converts the digitized voice samples into voice signals) and the host processor (414) (which performs AAL2 signaling and layer management functions). The receiver filters the AAL2 signaling and management packets from the AAL2 voice packets using a host programmable CID filter (550) and UUI filter (560). A match from either filter (550,560) enables the packet to be forwarded to the host processor (414). If no match is made in either filter (550,560), then a look-up is performed in a receive CID look-up table and the packet is forwarded to the DSP sub-system (412) on a look-up match.Type: GrantFiled: April 6, 2001Date of Patent: November 1, 2005Assignee: Texas Instruments IncorporatedInventors: Magnus Karlsson, Gregory Lee Christison, Norayda Humphrey
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Patent number: 6931012Abstract: The present invention provides an apparatus and system for high speed end-to-end telecommunication traffic using an Asynchronous Transfer Mode (ATM) architecture for convergence of video, data and voice in an SOHO application using a DSL router. An ATM processor (120) enables traffic shaping, and operation and maintenance processing within a single module. The ATM processor (120) further includes a processor (114) which executes firmware from a program memory (110). A register block (116) is provided for communicating setup and teardown notification, and OAM configuration to the processor (114) and a connection state RAM (112) provides for communicating connection configuration in which this information is used by the processor (114) when performing the functions of switching, QoS, and OAM. Transmit scheduler hardware (118) is provided for the scheduling of ATM cell transmission and is configured by the processor (114).Type: GrantFiled: April 6, 2001Date of Patent: August 16, 2005Assignee: Texas Instruments IncorporatedInventors: Magnus Karlsson, Gregory Lee Christison, Norayda Humphrey
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Patent number: 6915360Abstract: The present invention provides an apparatus and system for buffering data in a communication network with an arranged priority which enables traffic shaping. A cell buffer unit (600) is arranged with a plurality of queues (614) configured to store PDUs on-chip and off-chip. There are associated queues both on-chip and off-chip for each priority queue. A cell buffer controller (620) forwards PDUs to a predetermined priority queue and manages the transfer of PDUs off-chip when a priority queue on-chip is fully occupied. The controller (620) also manages the transfer of PDUs from the off-chip queue when the on-chip priority queue becomes less than fully occupied.Type: GrantFiled: April 6, 2001Date of Patent: July 5, 2005Assignee: Texas Instruments IncorporatedInventors: Magnus Karlsson, Gregory Lee Christison, Norayda Humphrey
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Publication number: 20040213157Abstract: The present invention provides an apparatus and system for high speed end-to-end telecommunication traffic using an Asynchronous Transfer Mode (ATM) architecture for convergence of video, data and voice in an SOHO application using a DSL router. An ATM processor (120) enables traffic shaping, and operation and maintenance processing within a single module. The ATM processor (120) further includes a processor (114) which executes firmware from a program memory (110). A register block (116) is provided for communicating setup and teardown notification, and OAM configuration to the processor (114) and a connection state RAM (12) provides for communicating connection configuration in which this information is used by the processor (114) when performing the functions of switching, QoS, and OAM. Transmit scheduler hardware (118) is provided for the scheduling of ATM cell transmission and is configured by the processor (114).Type: ApplicationFiled: April 6, 2001Publication date: October 28, 2004Inventors: Magnus Karlsson, Gregory Lee Christison, Norayda Humphrey
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Publication number: 20040202149Abstract: The present invention provides an apparatus, system and method for transmitting asynchronous transfer mode (ATM) data cells on an ATM adaptation layer (AAL) configured connection within an ATM system comprising a digital signal processor (DSP) sub-system (160) and a host processor (190). The transmitter interfaces directly with the DSP sub-system (160) (which converts the digitized voice samples into voice signals) and the host processor (190) (which performs AAL2 signaling and layer management functions). The transmitter is configured to interleave AAL2 voice packets from the DSP sub-system (160) and signaling and management packets from the host processor (190) on an ATM connection. Data is fetched by DMA(s) (415). A channel look-up table uses the DSP assigned voice channel as an index into the table to map a voice channel to the ATM connection.Type: ApplicationFiled: April 6, 2001Publication date: October 14, 2004Inventors: Magnus Karlsson, Gregory Lee Christison, Norayda Humphrey
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Patent number: 6804243Abstract: A Universal Serial Bus (USB) modem (14) in which reassembly and segmentation operations are performed outside of the host computer (12) is disclosed. A USB interface device (30) is coupled to a digital signal processor (DSP) (32) in the modem (14), and contains a shared memory (44) in which bulk endpoints (240) are established, at which ATM packet header and payload data are stored prior to transmission. An ATM transmit controller (132) retrieves the header portion of the ATM packet from a transmit endpoint (240) and stores the information in registers (252, 254, 256) in the ATM transmit controller (132). A four-byte ATM cell header is then transmitted to byte buffers (268) and to the DSP (32) for transmission over the communications facility. Afterwards, payload data is retrieved from the transmit endpoint (240) in shared memory (44), and forwarded to byte buffers (268) for transmission.Type: GrantFiled: February 18, 2000Date of Patent: October 12, 2004Assignee: Texas Instruments IncorporatedInventors: Norayda N. Humphrey, Magnus G Karlsson, Gregory Lee Christison
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Patent number: 6760333Abstract: A Universal Serial Bus (USB) modem (14) having two operating modes, namely Digital Subscriber Loop (DSL) mode and a voice-band mode, is disclosed. A USB interface device (30) is coupled to a digital signal processor (DSP) (32) and contains a shared memory (44) in which USB endpoints are established for data communication. In the DSL mode, an ATM receive controller (134) receives each ATM cell from the DSP (32) and interrogates the ATM cell header to determine the virtual connection to the corresponding cell, and then forwards the payload portion of the ATM cell, but not the ATM cell header. In the voice-band mode, the ATM receive controller (134) and ATM transmit controller (132) operate in a simple streaming mode. A host interface controller (135) is also provided, by way of which facsimile communications are carried out simultaneously with DSL communications, or in separate sessions relative to voice-band data communications.Type: GrantFiled: February 18, 2000Date of Patent: July 6, 2004Assignee: Texas Instruments IncorporatedInventors: Michael J. Moody, Magnus G. Karlsson, Norayda N. Humphrey, Gregory Lee Christison
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Patent number: 6671765Abstract: A USB function device (14) for coupling to a USB host (12). The USB function device (14), comprises circuitry (32) for providing a capability to the USB host, where the circuitry for the capability comprises an address space. The USB function device further comprises a USB interface circuit (136) coupled between the USB host (12) and the circuitry (32) for providing a capability to the USB host. The USB interface circuit comprises a memory area (106) comprising a code overlay endpoint (1061) accessible to the USB host for writing two or more code blocks to the code overlay endpoint. The USB interface circuit further comprises circuitry (150-163) for communicating a first of the code blocks from the code overlay endpoint to the address space and for subsequently communicating a second of the code blocks from the code overlay endpoint to the address space.Type: GrantFiled: February 18, 2000Date of Patent: December 30, 2003Assignee: Texas Instruments IncorporatedInventors: Magnus G. Karlsson, Gregory Lee Christison
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Publication number: 20030208552Abstract: The present invention provides an apparatus and system for buffering data in a communication network with an arranged priority which enables traffic shaping. A cell buffer unit (600) is arranged with a plurality of queues (614) configured to store PDUs on-chip and off-chip. There are associated queues both on-chip and off-chip for each priority queue. A cell buffer controller (620) forwards PDUs to a predetermined priority queue and manages the transfer of PDUs off-chip when a priority queue on-chip is fully occupied. The controller (620) also manages the transfer of PDUs from the off-chip queue when the on-chip priority queue becomes less than fully occupied.Type: ApplicationFiled: April 6, 2001Publication date: November 6, 2003Inventors: Magnus Karlsson, Gregory Lee Christison, Norayda Humphrey
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Patent number: 6523081Abstract: A USB function device (14) for coupling to a USB host (12). The USB function device (14) comprises circuitry (32) for providing a capability to the USB host, where the circuitry for providing a capability comprises an address space (VBUS). The USB function device (14) further comprises a USB interface circuit (30) coupled between the USB host and the circuitry for providing a capability to the USB host. The USB interface circuit (30) comprises a memory area (44, 106) comprising a write endpoint (1062) accessible to the USB host for writing a plurality of bytes to the memory area via the write endpoint. The plurality of bytes comprise data information and protocol information. The write endpoint comprises an endpoint-type other than a control-type endpoint. The USB interface circuit also comprises circuitry for decoding (166) the protocol information and circuitry for communicating the data information to the address space in response to the protocol information.Type: GrantFiled: February 18, 2000Date of Patent: February 18, 2003Assignee: Texas Instruments IncorporatedInventors: Magnus G. Karlsson, Michael J. Moody, Gregory Lee Christison
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Publication number: 20020146014Abstract: The present invention provides a unitary mechanism for high speed end-to-end telecommunication traffic using an Asynchronous Transfer Mode (ATM) architecture for convergence of video, data and voice in an SOHO application using a DSL router. An ATM module (101) for convergence of the telecommunications traffic includes an ATM processor (120) configured to perform QoS, OAM processing and switching in an ATM system. Function modules (102,104,105) and data ports (106,108) are configurable to transceive data, voice and video traffic in which the traffic is packetized in ATM data cells.Type: ApplicationFiled: April 6, 2001Publication date: October 10, 2002Inventors: Magnus Karlsson, Gregory Lee Christison, Norayda Humphrey
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Publication number: 20020146013Abstract: The present invention provides an apparatus, system and method for receiving asynchronous transfer mode (ATM) data cells on an ATM adaptation layer (AAL) configured connection within an ATM system comprising a digital signal processor (DSP) sub-system (412) and a host processor (414). The receiver interfaces directly with the DSP sub-system (412) (which converts the digitized voice samples into voice signals) and the host processor (414) (which performs AAL2 signaling and layer management functions). The receiver filters the AAL2 signaling and management packets from the AAL2 voice packets using a host programmable CID filter (550) and UUI filter (560). A match from either filter (550,560) enables the packet to be forwarded to the host processor (414). If no match is made in either filter (550,560), then a look-up is performed in a receive CID look-up table and the packet is forwarded to the DSP sub-system (412) on a look-up match.Type: ApplicationFiled: April 6, 2001Publication date: October 10, 2002Inventors: Magnus Karlsson, Gregory Lee Christison, Norayda Humphrey