Abstract: Error handling is simplified for a self-virtualizing IO resource that utilizes a physical function adjunct partition for a physical function in the self-virtualizing IO resource to coordinate error recovery for the self-virtualizing IO resource, by restarting each virtual function adjunct partition associated with that physical function to avoid the need to coordinate error recovery within the logical partitions to which such virtual function adjunct partitions are assigned.

Abstract: A computer-implemented method may include assigning an address translation table to a peripheral component interconnect host bridge and determining that an input/output adapter accessible to the peripheral component interconnect host bridge is configured as a virtualized adapter to provide a plurality of virtual functions to a plurality of logical partitions. In response to determining that the input/output adapter is configured as the virtualized adapter, the address translation table may be subdivided to enable the plurality of virtual functions to access the memory of at least one logical partition of the plurality of logical partitions.

Abstract: Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting the failure in the first link, the first set of bussed bits is exchanged between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device.

Abstract: Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device.

Abstract: In a method of handling errors in a digital system that includes a root complex in data communication with at least one endpoint, the endpoint including at least one advanced error reporting register, an error is detected by the endpoint. Error data indicative of the error is stored in an advanced error reporting register. An indication of which transaction caused the error is stored in a secondary location. An error message packet that includes the error data and the indication of which transaction caused the error is generated. The error message packet is transmitted to the root complex. The root complex is caused to take a preselected action in response to the error message packet.

Abstract: A data processing system includes a processor core, a system memory, coupled to the processor core, that includes an interrupt data structure including a plurality of entries each associated with a respective one of a plurality of interrupts. An input/output (I/O) subsystem including at least one I/O host bridge and a plurality of partitionable endpoints (PEs) each having an associated PE number. The I/O host bridge, responsive to receiving a message signaled interrupt (MSI) including at least a message address, determines from the message address a system memory address of a particular entry among the plurality of entries in the interrupt data structure, accesses the particular entry, and, based upon contents of the particular entry, validates authorization of an interrupt source to issue the MSI and presents an interrupt associated with the particular entry for service.

Abstract: In an embodiment, a south chip comprises a first virtual bridge connected to a shared egress port and a second virtual bridge also connected to the shared egress port. The first virtual bridge receives a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range from a first north chip. The second virtual bridge receives a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range from a second north chip. The first virtual bridge stores the first secondary bus identifier, the first subordinate bus identifier, and the first MMIO bus address range. The second virtual bridge stores the second secondary bus identifier, the second subordinate bus identifier, and the second MMIO bus address range. The first north chip and the second north chip are connected to the south chip via respective first and second point-to-point connections.

Abstract: In an embodiment, a translation of a physical bus number to a hierarchical bus number is written to a south chip. The south chip receives a configuration write command that comprises a physical bus number. The south chip sends the configuration write command to a device via the bus identified by the physical bus number, and the device stores the physical bus number in the device. In response to a received message from a device that comprises the physical bus number, the south chip replaces the physical bus number in the message with the hierarchical bus number. The south chip sends the message to a north chip via a point-to-point serial link. Both the physical bus number and the hierarchical bus number identify a bus with which the device connects to a bridge in the south chip.

Abstract: In an embodiment, a translation of a hierarchical bus number to a physical bus number and a bridge identifier of a bridge are written to a north chip. A request is received that comprises an identifier of a destination. A determination is made that the identifier comprises the hierarchical bus number. In response to the determination, the identifier of the destination is replaced in the request with the physical bus number and the bridge identifier. The request is sent to the bridge identified by the bridge identifier. A south chip comprises the bridge, and the south chip is connected to the north chip via a point-to-point serial link. The physical bus number identifies a bus that connects the bridge to a device. The request comprises a configuration write request that requests a write of data to the device.

Abstract: In an embodiment, a translation of a hierarchical MMIO address range to a physical MMIO address range and an identifier of a bridge in a south chip are written to a north chip. A transaction is received that comprises a hierarchical MMIO address. The hierarchical MMIO address that is within the hierarchical MMIO address range is replaced in the transaction with the identifier of the bridge and with a physical MMIO address that is within the physical MMIO address range in the south chip. The transaction is sent to the device that is connected to the bridge in the south chip. The physical MMIO address range specifies a range of physical MMIO addresses in memory in the device.

Abstract: Method, apparatus and system for isolating input/output adapter error domains in a data processing system. Errors occurring in one input/output adapter are isolated from other input/output adapters of the data processing system by functionality in a host bridge that connects the input/output adapters to a system bus of the data processing system, thus permitting the use of low cost, industry standard switches and bridges external to the host bridge.

Abstract: In a method of handling errors in a digital system that includes a root complex in data communication with at least one endpoint, the endpoint including at least one advanced error reporting register, an error is detected by the endpoint. Error data indicative of the error is stored in an advanced error reporting register. An indication of which transaction caused the error is stored in a secondary location. An error message packet that includes the error data and the indication of which transaction caused the error is generated. The error message packet is transmitted to the root complex. The root complex is caused to take a preselected action in response to the error message packet.

Abstract: Methods, systems, and products are disclosed for operating Peripheral Component Interconnect (‘PCI’) Express resources in a logically partitioned computing system that include: allocating, by a hypervisor installed on the computing system, a PCI Express adapter installed in the computing system to a logical partition of the computing system, including establishing a data communication path between a processor of the computing system and the PCI Express adapter, the data communication path including a link between a PCI Express root complex and the PCI Express adapter; and administering, by the hypervisor for the logical partition, the PCI Express root complex and the link between the PCI Express root complex and the PCI Express adapter.

Abstract: Methods, systems, and products are disclosed for operating Peripheral Component Interconnect (‘PCI’) Express resources in a logically partitioned computing system that include: allocating, by a hypervisor installed on the computing system, a PCI Express adapter installed in the computing system to a logical partition of the computing system, including establishing a data communication path between a processor of the computing system and the PCI Express adapter, the data communication path including a link between a PCI Express root complex and the PCI Express adapter; and administering, by the hypervisor for the logical partition, the PCI Express root complex and the link between the PCI Express root complex and the PCI Express adapter.

Abstract: Embodiments are provided in which a method is described for a processor to perform a task of accessing a PCI-X device via a PCI-X bridge, the PCI-X bridge including a processing circuit. The processor builds M read/write control blocks (RWCBs), M being a positive integer. Then, the processor signals the processing circuit and switches to another task. In response, the processing circuit fetches and processes the M RWCBs, one RWCB at a time, to access the PCI-X device. After processing the M RWCBs, the processing circuit interrupts the processor. In response, the processor obtains the result of the processing of the M RWCBs.

Abstract: Embodiments are provided in which a method is described for a processor to perform a task of accessing a PCI-X device via a PCI-X bridge, the PCI-X bridge including a processing circuit. The processor builds M read/write control blocks (RWCBs), M being a positive integer. Then, the processor signals the processing circuit and switches to another task. In response, the processing circuit fetches and processes the M RWCBs, one RWCB at a time, to access the PCI-X device. After processing the M RWCBs, the processing circuit interrupts the processor. In response, the processor obtains the result of the processing of the M RWCBs.

Abstract: A method and apparatus for performing direct memory address (DMA) operations between a requestor and responder device by prestoring, for each device, a logical token and offset value which is recognizable by the device as an indicia to identify one or more local memory addresses within the device, and initiating a DMA operation within the requestor device by the requestor device transferring the token and offset value to the responder device, the responder device identifying a responder device local memory address by translation of the token and offset value, and the responder device accessing the identified responder local memory address for data transfer, associated with the token and offset, and the requestor device identifying a requestor device local memory address for completing the data transfer.

Abstract: Dynamic switch protocols are implemented on a token bus protocol in a shared medium network to improve the basic token bus functional capabilities and link utilization, and to produce a uniform transaction protocol that supports both token bus and dynamic switch networks. Frame formats common to both token bus and dynamic switch protocols are utilized, and circuit switched protocols are superimposed on a token bus protocol in interlocked and data transmissions to establish a circuit switched path between a token holder sender node and a destination node. An initial frame transmission uses a normal link header and establishes the circuit switched path between the sender node and the destination node. Subsequent data frames contain no link header information, thereby improving transmission efficiency, and the last frame in such a transmission disconnects the switched circuit path, thereby allowing other transmissions to resume.