Patents by Inventor Gregory T. Elkins

Gregory T. Elkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8769219
    Abstract: A storage controller including a processor and a memory controller. The processor is configured to generate a command corresponding to a first write operation and a second write operation, in which the first write operation is contiguous to the second write operation, and the first write operation is received prior to the second write operation. The command arranges the second write operation prior to the first write operation. The memory controller is configured to, in response to the command, execute each of the first write operation and the second write operation. The second write operation is executed by the memory controller prior to the first write operation.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: July 1, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Arie L. Krantz, Kha Nguyen, Gregory T. Elkins
  • Publication number: 20120185655
    Abstract: A controller for a disk drive includes first memory storing first write operations and second write operations received in a first order. A processor arranges the first write operations and the second write operations in a second order based on respective track sectors associated with the first and the second write operations. The second order is different than the first order. A memory controller transfers write operation data corresponding to the first write operations and the second write operations to a disk formatter in the second order in response to a single command from the processor.
    Type: Application
    Filed: March 26, 2012
    Publication date: July 19, 2012
    Inventors: Arie L. Krantz, Kha Nguyen, Gregory T. Elkins
  • Patent number: 8145835
    Abstract: A controller for a disk drive including a buffer memory controller and a processor. The buffer memory controller is configured to receive a first write operation and a second write operation in a first order, store the first write operation and the second write operation in a buffer memory, and transfer write data corresponding to the first write operation and the second write operation in a second order that is different than the first order in response to a single command. The processor is configured to arrange the first write operation and the second write operation in the second order and issue the single command according to the second order.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: March 27, 2012
    Assignee: Marvell World Trade, Ltd.
    Inventors: Arie L. Krantz, Kha Nguyen, Gregory T. Elkins
  • Publication number: 20110029727
    Abstract: A controller for a disk drive includes first memory storing first write operations and second write operations received in a first order. A processor arranges the first write operations and the second write operations in a second order based on respective track sectors associated with the first and the second write operations. The second order is different than the first order. A memory controller transfers write operation data corresponding to the first write operations and the second write operations to a disk formatter in the second order in response to a single command from the processor.
    Type: Application
    Filed: October 12, 2010
    Publication date: February 3, 2011
    Inventors: Arie L. Krantz, Kha Nguyen, Gregory T. Elkins
  • Patent number: 7814271
    Abstract: A controller for a disk drive includes first memory storing first write operations and second write operations received in a first order. A processor arranges the first write operations and the second write operations in a second order based on respective track sectors associated with the first and the second write operations. The second order is different than the first order. A memory controller transfers write operation data corresponding to the first write operations and the second write operations to a disk formatter in the second order in response to a single command from the processor.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: October 12, 2010
    Assignee: Marvell World Trade Ltd.
    Inventors: Arie L. Krantz, Kha Nguyen, Gregory T. Elkins
  • Publication number: 20090150607
    Abstract: A controller for a disk drive includes first memory storing first write operations and second write operations received in a first order. A processor arranges the first write operations and the second write operations in a second order based on respective track sectors associated with the first and the second write operations. The second order is different than the first order. A memory controller transfers write operation data corresponding to the first write operations and the second write operations to a disk formatter in the second order in response to a single command from the processor.
    Type: Application
    Filed: December 18, 2008
    Publication date: June 11, 2009
    Inventors: Arie L. Krantz, Kha Nguyen, Gregory T. Elkins
  • Patent number: 7484037
    Abstract: A memory controller for a disk controller comprises a first memory that receives first and second write operations in a first order and that stores the first and second write operations and corresponding write operation data. A second memory stores a corresponding address for each of the write operations, wherein the corresponding addresses identify a location of the write operation data stored in the first memory. Controller logic determines whether the first write operation and the second write operation write data to a same track of a disk and transfers the write operation data from the first memory to a third memory in a second order when the first write operation and the second write operation write data to the same track, wherein the second order is different from the first order.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: January 27, 2009
    Assignee: Marvell International Ltd.
    Inventors: Arie L. Krantz, Kha Nguyen, Gregory T. Elkins
  • Patent number: 7103715
    Abstract: A buffer memory controller comprises a first memory configured to buffer write operation data between a write head and a second memory that stores write operation data corresponding to first and second write operations. A first memory location identifies a location of write operation data that corresponds to the first write operation stored within the second memory. A second memory location identifies a location of write operation data that corresponds to the second write operation stored within the second memory. Controller logic determines whether the first write operation and the second write operation write data to the same track. The controller logic transfers the data of the first write operation and the second write operation in an order other than the order in which the second memory received the first and second write operations when the first write operation and the second write operation write data to the same track.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: September 5, 2006
    Assignee: Marvell World Trade Ltd.
    Inventors: Arie L. Krantz, Kha Nguyen, Gregory T. Elkins
  • Patent number: 6826650
    Abstract: A hard disk unit includes a disk, controller microprocessor, host bus interface, buffer memory, buffer memory controller and disk formatter. The bus interface receives write operations, and the corresponding write operation data is stored in the buffer memory. The buffer memory controller also includes a set of address registers and a set of block count registers. The microprocessor loads the address registers with the buffer memory addresses of data of multiple write operations and loads the block count registers with the size of the corresponding data. The microprocessor then issues a single command to the buffer memory controller to transfer the data from the buffer memory to the disk formatter. The address registers and block count registers enable the data of multiple write operations to be transferred and written to a disk in an order other than the order in which the write operations were received at the bus interface.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: November 30, 2004
    Assignee: QLogic Corporation
    Inventors: Arie L. Krantz, Kha Nguyen, Gregory T. Elkins
  • Patent number: 6470461
    Abstract: In a disk drive, a disk drive controller circuit and method keep track of defective and/or undesired sectors on a disk and skip such defective or undesired sectors during a read or write operation requested by a host system. A microprocessor is programmed to respond to a read or write command from the host system by converting a list of sectors to be skipped to an address and range format suitable for loading a set of registers within the controller circuit. The microprocessor loads the set of registers, and the controller circuit compares each sector identified by the read or write command with the contents of the set of registers. If a sector identified by the read or write command matches one of the sectors to be skipped, the controller circuit skips that sector during the read or write operation.
    Type: Grant
    Filed: June 7, 1999
    Date of Patent: October 22, 2002
    Assignee: QLogic Corporation
    Inventors: Daniel R. Pinvidic, Gregory T. Elkins, Stanley K. Cheong