Patents by Inventor Griselda Bonilla
Griselda Bonilla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140070362Abstract: E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.Type: ApplicationFiled: November 13, 2013Publication date: March 13, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda BONILLA, Kaushik CHANDA, Samuel S. CHOI, Ronald G. FILIPPI, Stephan GRUNOW, Naftali E. LUSTIG, Andrew H. SIMON
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Publication number: 20140028325Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.Type: ApplicationFiled: September 30, 2013Publication date: January 30, 2014Applicant: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
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Publication number: 20140021622Abstract: A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.Type: ApplicationFiled: July 20, 2012Publication date: January 23, 2014Applicant: international Business Machines CorporationInventors: Griselda Bonilla, Timothy H. Daubenspeck, Mark C.H. Lamorey, Howard S. Landis, Xiao Hu Liu, David L. Questad, Thomas M. Shaw, David B. Stone
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Patent number: 8633707Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.Type: GrantFiled: March 29, 2011Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: Ronald G. Filippi, Griselda Bonilla, Kaushik Chanda, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
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Patent number: 8623761Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.Type: GrantFiled: September 6, 2012Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Christos D. Dimitrakopoulos, Alfred Grill, James B. Hannon, Qinghuang Lin, Deborah A. Neumayer, Satoshi Oida, John A. Ott, Dirk Pfeiffer
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Publication number: 20130307151Abstract: A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer.Type: ApplicationFiled: May 16, 2012Publication date: November 21, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Junjing Bao, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
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Publication number: 20130299988Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.Type: ApplicationFiled: May 10, 2012Publication date: November 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Christos D. Dimitrakopoulos, Alfred Grill, James B. Hannon, Qinghuang Lin, Deborah A. Neumayer, Satoshi Oida, John A. Ott, Dirk Pfeiffer
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Publication number: 20130302978Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.Type: ApplicationFiled: September 6, 2012Publication date: November 14, 2013Applicant: International Business Machines CorporationInventors: Griselda Bonilla, Christos D. Dimitrakopoulos, Alfred Grill, James B. Hannon, Qinghuang Lin, Deborah A. Neumayer, Satoshi Oida, John A. Ott, Dirk Pfeiffer
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Publication number: 20130234284Abstract: A fuse structure includes within an aperture within a dielectric layer located over a substrate that exposes a conductor contact layer within the substrate a seed layer interposed between the conductor contact layer and another conductor layer. The seed layer includes a doped copper material that includes a dopant immobilized predominantly within the seed layer. The fuse structure may be severed while not severing a conductor interconnect structure also located over the substrate that exposes a second conductor contact layer within a second aperture. In contrast with the fuse structure that includes the doped seed layer having the immobilized dopant, the interconnect structure includes a doped seed layer having a mobile dopant.Type: ApplicationFiled: March 8, 2012Publication date: September 12, 2013Applicant: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Samuel Sung Shik Choi, Ronald G. Filippi, Stephan Grunow, Naftali Eliahu Lustig, Andrew H. Simon
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Publication number: 20130214894Abstract: Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.Type: ApplicationFiled: February 17, 2012Publication date: August 22, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon
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Publication number: 20130176073Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.Type: ApplicationFiled: January 11, 2012Publication date: July 11, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Junjing Bao, Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald Filippi, Stephan Grunow, Naftali E. Lustig, Dan Moy, Andrew H. Simon
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Publication number: 20130175697Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.Type: ApplicationFiled: January 5, 2012Publication date: July 11, 2013Applicant: International Business Machines CorporationInventors: Son Van Nguyen, Griselda Bonilla, Alfred Grill, Thomas J. Haigh, JR., Satyanarayana V. Nitta
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Patent number: 8481423Abstract: Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.Type: GrantFiled: September 19, 2007Date of Patent: July 9, 2013Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.Inventors: John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Dubois, Daniel C. Edelstein, Alfred Grill, Elbert Huang, Robert D. Miller, Satya V. Nitta, Sampath Purushothaman, E. Todd Ryan, Muthumanickam Sankarapandian, Terry A. Spooner, Willi Volksen
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Patent number: 8470706Abstract: Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.Type: GrantFiled: September 1, 2012Date of Patent: June 25, 2013Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.Inventors: John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Dubois, Daniel C. Edelstein, Alfred Grill, Elbert Huang, Robert D. Miller, Satya V. Nitta, Sampath Purushothaman, E. Todd Ryan, Muthumanickam Sankarapandian, Terry A. Spooner, Willi Volksen
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Publication number: 20130127584Abstract: A metal fuse structure using redundant vias. The redundant vias are formed on one metal level in a stacked via metal fuse structure to force failures to occur in the metal level that does not have the redundant vias. The metal fuse structure includes: a first dielectric layer having a metal feature; a second dielectric layer having a first metal connector embedded therein; and a third dielectric layer having a second metal connector embedded therein. The metal connectors include at least one via and one line, and at least one metal connector has at least two vias.Type: ApplicationFiled: November 17, 2011Publication date: May 23, 2013Applicant: International Business Machines CorporationInventors: Ronald G. Filippi, Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon
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Patent number: 8421239Abstract: A method for forming crenulated conductors and a device having crenulated conductors includes forming a hardmask layer on a dielectric layer, and patterning the hardmask layer. Trenches are etched in the dielectric layer using the hardmask layer such that the trenches have shallower portions and deeper portions alternating along a length of the trench. A conductor is deposited in the trenches such that crenulated conductive lines are formed having different depths periodically disposed along the length of the conductive line.Type: GrantFiled: March 16, 2010Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Elbert E. Huang, Satyanarayana V. Nitta, Shom Ponoth
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Publication number: 20130049207Abstract: A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.Type: ApplicationFiled: August 30, 2011Publication date: February 28, 2013Applicant: International Business Machines CorporationInventors: Eric G. Liniger, Griselda Bonilla, Pak Leung, Stephan A. Cohen, Stephen M. Gates, Thomas M. Shaw
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Publication number: 20120329269Abstract: Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.Type: ApplicationFiled: September 1, 2012Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Dubois, Daniel C. Edelstein, Alfred Grill, Elbert Huang, Robert D. Miller, Satya V. Nitta, Sampath Purushothaman, E. Todd Ryan, Muthumanickam Sankarapandian, Terry A. Spooner, Willi Volksen
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Publication number: 20120326269Abstract: E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.Type: ApplicationFiled: June 21, 2011Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: GRISELDA BONILLA, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon
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Patent number: 8298948Abstract: A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also results in the deposition of stray metal material on the surface of the dielectric substrate, and etching with an isotropic etching process to remove a portion of the metal film layer and the stray metal material on the surface of the dielectric substrate, wherein the metal film layer is deposited at an initial thickness sufficient to leave a metal film layer cap remaining on the copper line following the removal of the stray metal material.Type: GrantFiled: November 6, 2009Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, David L. Rath, Sujatha Sankaran, Andrew H. Simon, Theodorus Eduardus Standaert, Chih-Chao Yang