Patents by Inventor Guan-Wei Huang

Guan-Wei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230260849
    Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 17, 2023
    Inventors: Guan-Lin Chen, Chih-Hao Wang, Ching-Wei Tsai, Shi Ning Ju, Jui-Chien Huang, Kuo-Cheng Chiang, Kuan-Lun Cheng
  • Publication number: 20230095609
    Abstract: A system, includes, a semiconductor processing unit, an Automated Materials Handling System (AMHS) vehicle, and a warehouse apparatus, wherein the warehouse apparatus comprises at least one input port, at least one output port, and at least one load/unload port, wherein the warehouse apparatus is configured to perform one of the following: receiving a plurality of tray cassette containers from the AMHS vehicle at the at least one input port, transporting at least one tray cassette in each of a plurality of tray cassette containers to the at least one load/unload port via the at least one input port, transporting at least one first tray from the at least one tray cassette to the semiconductor processing unit via a tray feeder conveyor, and receiving at least one second tray from the semiconductor processing unit via the tray feeder conveyor.
    Type: Application
    Filed: December 2, 2022
    Publication date: March 30, 2023
    Inventors: Tsung-Sheng Kuo, Yang-Ann Chu, Chih-Hung Huang, Guan-Wei Huang, Jiun-Rong Pai, Hsuan Lee
  • Publication number: 20230054372
    Abstract: A semiconductor structure that includes a first semiconductor fin and a second semiconductor fin disposed over a substrate and adjacent to each other, a metal gate stack disposed over the substrate, and source/drain features disposed in each of the first semiconductor fin and the second semiconductor fin to engage with the metal gate stack. The metal gate stack includes a first region disposed over the first semiconductor fin, a second region disposed over the second semiconductor fin, and a third region connecting the first region to the second region in a continuous profile, where the first region is defined by a first gate length and the second region is defined by a second gate length less than the first gate length.
    Type: Application
    Filed: August 20, 2021
    Publication date: February 23, 2023
    Inventors: Guan-Wei Huang, Yu-Shan Lu, Yu-Bey Wu, Jiun-Ming Kuo, Yuan-Ching Peng
  • Publication number: 20230058811
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Application
    Filed: November 7, 2022
    Publication date: February 23, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Patent number: 11527448
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Grant
    Filed: December 27, 2020
    Date of Patent: December 13, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Patent number: 11527425
    Abstract: A system, includes, a semiconductor processing unit, an Automated Materials Handling System (AMHS) vehicle, and a warehouse apparatus, wherein the warehouse apparatus comprises at least one input port, at least one output port, and at least one load/unload port, wherein the warehouse apparatus is configured to perform one of the following: receiving a plurality of tray cassette containers from the AMHS vehicle at the at least one input port, transporting at least one tray cassette in each of a plurality of tray cassette containers to the at least one load/unload port via the at least one input port, transporting at least one first tray from the at least one tray cassette to the semiconductor processing unit via a tray feeder conveyor, and receiving at least one second tray from the semiconductor processing unit via the tray feeder conveyor.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Sheng Kuo, Yang-Ann Chu, Chih-Hung Huang, Guan-Wei Huang, Jiun-Rong Pai, Hsuan Lee
  • Publication number: 20220359248
    Abstract: In certain embodiments, a workstation includes: a cleaning station configured to clean a die vessel, wherein the die vessel is configured to secure a semiconductor die; an inspection station configured to inspect the die vessel after cleaning to determine whether the die vessel is identified as passing inspection; and a conveyor configured to move the die vessel between the cleaning station and the inspection station.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Tsung-Sheng KUO, Guan-Wei HUANG, Chih-Hung HUANG, Yang-Ann CHU, Hsu-Shui LIU, Jiun-Rong PAI
  • Patent number: 11488848
    Abstract: In certain embodiments, a workstation includes: a cleaning station configured to clean a die vessel, wherein the die vessel is configured to secure a semiconductor die; an inspection station configured to inspect the die vessel after cleaning to determine whether the die vessel is identified as passing inspection; and a conveyor configured to move the die vessel between the cleaning station and the inspection station.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Sheng Kuo, Guan-Wei Huang, Chih-Hung Huang, Yang-Ann Chu, Hsu-Shui Liu, Jiun-Rong Pai
  • Patent number: 11271090
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a first gate structure on the NMOS region and a second gate structure on the PMOS region; forming a seal layer on the first gate structure and the second gate structure; forming a first lightly doped drain (LDD) adjacent to the first gate structure; forming a second LDD adjacent to the second gate structure; and performing a soak anneal process to boost an oxygen concentration of the seal layer for reaching a saturation level.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: March 8, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ming Kuo, Fu-Jung Chuang, Po-Jen Chuang, Chia-Wei Chang, Guan-Wei Huang, Chia-Yuan Chang
  • Publication number: 20210320187
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a first gate structure on the NMOS region and a second gate structure on the PMOS region; forming a seal layer on the first gate structure and the second gate structure; forming a first lightly doped drain (LDD) adjacent to the first gate structure; forming a second LDD adjacent to the second gate structure; and performing a soak anneal process to boost an oxygen concentration of the seal layer for reaching a saturation level.
    Type: Application
    Filed: May 6, 2020
    Publication date: October 14, 2021
    Inventors: Chia-Ming Kuo, Fu-Jung Chuang, Po-Jen Chuang, Chia-Wei Chang, Guan-Wei Huang, Chia-Yuan Chang
  • Publication number: 20210202277
    Abstract: A system, includes, a semiconductor processing unit, an Automated Materials Handling System (AMHS) vehicle, and a warehouse apparatus, wherein the warehouse apparatus comprises at least one input port, at least one output port, and at least one load/unload port, wherein the warehouse apparatus is configured to perform one of the following: receiving a plurality of tray cassette containers from the AMHS vehicle at the at least one input port, transporting at least one tray cassette in each of a plurality of tray cassette containers to the at least one load/unload port via the at least one input port, transporting at least one first tray from the at least one tray cassette to the semiconductor processing unit via a tray feeder conveyor, and receiving at least one second tray from the semiconductor processing unit via the tray feeder conveyor.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Inventors: Tsung-Sheng KUO, Yang-Ann CHU, Chih-Hung HUANG, Guan-Wei HUANG, Jiun-Rong PAI, Hsuan LEE
  • Publication number: 20210118750
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Application
    Filed: December 27, 2020
    Publication date: April 22, 2021
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Publication number: 20210066104
    Abstract: A system and computer-implemented method are provided for manufacturing a semiconductor electronic device. An assembler receives a jig and a boat supporting a die. The assembler includes a separator that separates the jig into a first jig portion and a second jig portion and a loader that positions the boat between the first jig portion and the second jig portion. A robot receives an assembly prepared by the assembler and manipulates a locking system that fixes an alignment of the boat relative to the first jig portion and the second jig portion to form a locked assembly. A process chamber receives the locked assembly and subjects the locked assembly to a fabrication operation.
    Type: Application
    Filed: July 27, 2020
    Publication date: March 4, 2021
    Inventors: Tsung-Sheng KUO, Chih-Hung HUANG, Guan-Wei HUANG, Ping-Yung YEN, Hsuan LEE, Jiun-Rong PAI
  • Patent number: 10910277
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: February 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Patent number: 10892194
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: January 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Publication number: 20200328126
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Patent number: 10741455
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: August 11, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Publication number: 20200194316
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Publication number: 20200176331
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Patent number: 10607897
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 31, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng