Patents by Inventor Guang Chang Ye

Guang Chang Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10871923
    Abstract: A program operation is executed on a memory sub-system. During execution of the program operation, a request to execute a read operation on the memory sub-system is received. In response to receiving the request, a program suspend operation to suspend the program operation is executed. The read operation is executed on the memory sub-system in response to a completion of the program suspend operation. In response to completion of the read operation, a program resume operation is executed. A program suspend delay period is established following execution of the program resume operation during which a subsequent read operation is stored in a queue.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jiangang Wu, Sampath K. Ratnam, Yang Zhang, Guang Chang Ye, Kishore Kumar Muchherla, Hong Lu, Karl D. Schuh, Vamsi Pavan Rayaprolu
  • Publication number: 20200285416
    Abstract: A program operation is executed on a memory sub-system. During execution of the program operation, a request to execute a read operation on the memory sub-system is received. In response to receiving the request, a program suspend operation to suspend the program operation is executed. The read operation is executed on the memory sub-system in response to a completion of the program suspend operation. In response to completion of the read operation, a program resume operation is executed. A program suspend delay period is established following execution of the program resume operation during which a subsequent read operation is stored in a queue.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Inventors: Jiangang Wu, Sampath K. Ratnam, Yang Zhang, Guang Chang Ye, Kishore Kumar Muchherla, Hong Lu, Karl D. Schuh, Vamsi Pavan Rayaprolu
  • Publication number: 20100306293
    Abstract: A Galois field multiplier is provided, comprising a multiplication circuit for inputting two m bits binary multiplicators and outputting their product, wherein m is an integral power of 2, and the output of said multiplication circuit is consisted of a high bits portion output and a low bits portion output; a memory for storing a Galois field multiplication coefficient array calculated from a selected Galois field primitive polynomial; a first module for performing operation on the output of said multiplication circuit and the Galois field multiplication coefficient array stored in said memory to obtain the product of the two m bits binary multiplicators over Galois field. The Galois field multiplier has small hardware footprint, short response latency and strong universality.
    Type: Application
    Filed: May 12, 2010
    Publication date: December 2, 2010
    Applicant: International Business Machines Corporation
    Inventors: Yu Fei Li, Yong Lu, Guang Chang Ye, Fan Zhou