Abstract: The present technology is generally related to the process of converting plastics to olefin and aromatics through pyrolysis, wherein the process of producing at least one or more of olefins and aromatic compounds from a plastic feedstock includes: contacting a plastic feedstock and a catalyst composition at a temperature from about 450° C. to about 650° C. in a conical spouted bed reactor and for a time period sufficient to allow at least a portion of the plastic feedstock to be converted to at least one or more olefins and aromatic compounds and wherein the catalyst composition includes greater than about 40% w/w of ZSM-5, based on the total weight of the catalyst composition.

Abstract: A semiconductor device includes: a substrate; a seed layer disposed on the substrate; a compound semiconductor stack layer disposed on the seed layer; and a source metal layer and a drain metal layer disposed on the compound semiconductor stack layer. The semiconductor device further includes a conductive layer at least partially covering the source metal layer and the drain metal layer, and covering opposing side surfaces of the seed layer and opposing side surfaces of the compound semiconductor stack layer. The conductive layer electrically connects the seed layer and the source metal layer.

Abstract: A system for converting plastic includes a catalyst regenerator, a feeder containing plastic feedstock, a first conical spouted bed reactor stage in fluid communication with the catalyst regenerator and in fluid communication with the feeder, and a second conical spouted bed reactor stage in fluid communication with the first conical spouted bed reactor stage.

Abstract: A semiconductor device includes: a substrate; a seed layer disposed on the substrate; a compound semiconductor stack layer disposed on the seed layer; and a source metal layer and a drain metal layer disposed on the compound semiconductor stack layer. The semiconductor device further includes a conductive layer at least partially covering the source metal layer and the drain metal layer, and covering opposing side surfaces of the seed layer and opposing side surfaces of the compound semiconductor stack layer. The conductive layer electrically connects the seed layer and the source metal layer.

Abstract: A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.

Abstract: A semiconductor device includes: a substrate; a seed layer disposed on the substrate; a compound semiconductor stack layer disposed on the seed layer; and a source metal layer and a drain metal layer disposed on the compound semiconductor stack layer. The semiconductor device further includes a conductive layer at least partially covering the source metal layer and the drain metal layer, and covering opposing side surfaces of the seed layer and opposing side surfaces of the compound semiconductor stack layer. The conductive layer electrically connects the seed layer and the source metal layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a lead frame and a sub-substrate disposed on the lead frame, wherein the thickness of the sub-substrate is between 0 and 0.5 ?m. The semiconductor structure also includes an epitaxial layer disposed on the sub-substrate. The epitaxial layer includes a buffer layer, a channel layer and a barrier layer. The buffer layer is disposed between the sub-substrate and the channel layer. The channel layer is disposed between the buffer layer and the barrier layer. The semiconductor structure further includes a device layer disposed on the barrier layer and an interconnector structure electrically connected to the epitaxial layer and/or the device layer by a through hole.

Abstract: A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.

Abstract: An electrocardiogram detector including a pad, an electrical connection unit, a plurality of retaining members, and a plurality of electrode pieces is disclosed. The pad has a first face, a second face, and a plurality of through-holes. The electrical connection unit has an electrical connection port and a plurality of conducting lines electrically connected to the electrical connection port. The plurality of conducting lines is arranged on the first face of the pad. The plurality of retaining members is fixed to the first face of the pad and electrically connected to the plurality of conducting lines. The plurality of electrode pieces is electrically connected to the plurality of retaining members. The plurality of electrode pieces is fixed by the plurality of retaining members. In this arrangement, convenient operation of the electrocardiogram detector is improved.

Abstract: A system and method are disclosed for adaptive authentication. An access control system stores policies for an enterprise, where each policy specifies a type of access control. The type of access control includes one or more security rules, which may specify authentication procedures, allowable behaviors, or both. The access control system stores a mapping from contexts of requests to interact with applications and access control policies. When a user requests access to an application associated with the enterprise via a client, the access control system receives the context of the request. The access control system selects an access control policy for the context of the request. The access control system sends access control information from the access control policy selected to the client. The client interacts with the user to perform the authentication.

Abstract: An enhancement mode GaN transistor having a gate pGaN structure having a thickness which avoids dielectric failure. In one embodiment, this thickness is in the range of 400 ? to 900 ?. In a preferred embodiment, the thickness is 600 ?.

Abstract: An integrated semiconductor device which includes a substrate layer, a buffer layer formed on the substrate layer, a gallium nitride layer formed on the buffer layer, and a barrier layer formed on the gallium nitride layer. Ohmic contacts for a plurality of transistor devices are formed on the barrier layer. Specifically, a plurality of first ohmic contacts for the first transistor device are formed on a first portion of the surface of the barrier layer, and a plurality of second ohmic contacts for the second transistor device are formed on a second portion of the surface of the barrier layer. In addition, one or more gate structures formed on a third portion of the surface of the barrier between the first and second transistor devices. Preferably, the one or more gate structures and the spaces between the gate structures and the source contacts of the transistor devices collectively form an isolation region that electrically isolates the first transistor device from the second transistor device.

Abstract: A method for forming an enhancement mode GaN HFET device with an isolation area that is self-aligned to a contact opening or metal mask window. Advantageously, the method does not require a dedicated isolation mask and the associated process steps, thus reducing manufacturing costs. The method includes providing an EPI structure including a substrate, a buffer layer a GaN layer and a barrier layer. A dielectric layer is formed over the barrier layer and openings are formed in the dielectric layer for device contact openings and an isolation contact opening. A metal layer is then formed over the dielectric layer and a photoresist film is deposited above each of the device contact openings. The metal layer is then etched to form a metal mask window above the isolation contact opening and the barrier and GaN layer are etched at the portion that is exposed by the isolation contact opening in the dielectric layer.

Abstract: Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability.

Abstract: A battery cover includes an inner assembly and an outer assembly. The inner assembly includes an upper board defining an L-shaped groove, a bottom board screwed connected with the upper board; and a metal dome fixed between the upper board and the bottom board to pass throughout the bottom board for contacting the battery compartment. The outer assembly includes a front cover defining a first opening thereon, a slide button receiving in the first opening and the L-shaped groove of the upper board to slidably move along the L-shaped groove.

Abstract: An enhancement mode gallium nitride (GaN) transistor with a Mg doped layer and a Mg growth interruption (diffusion barrier) layer to trap excess or residual Mg dopant. The Mg growth interruption (diffusion barrier) layer is formed by growing GaN, stopping the supply of gallium while maintaining a supply of ammonia or other nitrogen containing source to form a layer of magnesium nitride (MgN), and then resuming the flow of gallium to form a GaN layer to seal in the layer of MgN.

Abstract: An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.

Abstract: A MISFET, such as a GaN transistor, with low gate leakage. In one embodiment, the gate leakage is reduced with a compensated GaN layer below the gate contact and above the barrier layer. In another embodiment, the gate leakage is reduced by employing a semi-insulating layer below the gate contact and above the barrier layer.

Abstract: Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability.