Patents by Inventor Guangshuai WANG

Guangshuai WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11901375
    Abstract: An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: February 13, 2024
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yongbo Ju, Pengfei Cui, Jian Sun, Deshuai Wang, Xiangkai Shen, Jianbin Gao, Jiannan Wang, Guangshuai Wang
  • Publication number: 20230112991
    Abstract: Disclosed is a method of high-precision 3D reconstruction of existing railway track lines based on UAV multi-view images, including: acquiring initial data, acquiring a UAV image rail top centerline, calculating a rail top centerline based on a nonlinear least squares method, and calculating three-dimensional coordinates of the rail centerline. Based on the multi-view geometry principle in computer vision and photogrammetry, object space coordinates of the line can be directly calculated by using image information, which does not require outdoor workers to work online and can effectively improve the safety of railway operation line surveying and mapping. Therefore, this method has important engineering application value and application prospect.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 13, 2023
    Applicant: CHINA RAILWAY DESIGN CORPORATION
    Inventors: Guangshuai WANG, Jiwei DENG, Wenfeng GAO, Hai ZHAO, Guanjun ZHANG, Kai WANG, Yingjie ZHANG, Huxiao NIE, Wenteng ZHANG, Liang YUE, Yuhui GE, Shuai GAO, Luoming ZHAO
  • Publication number: 20220367530
    Abstract: An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.
    Type: Application
    Filed: April 13, 2021
    Publication date: November 17, 2022
    Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yongbo JU, Pengfei CUI, Jian SUN, Deshuai WANG, Xiangkai SHEN, Jianbin GAO, Jiannan WANG, Guangshuai WANG
  • Publication number: 20220291538
    Abstract: An array substrate has a display area and a bezel area located on at least one side of the display area. The bezel area includes a bonding region. The array substrate includes a substrate, a plurality of signal lines, a plurality of conductive bumps, and an insulating layer. The signal lines are disposed on the substrate. The conductive blocks are disposed on a portion of the substrate located in the bonding region, and a conductive bump is connected to at least one signal line. The insulating layer covers the plurality of signal lines and is located between every two adjacent conductive bumps. The conductive bump includes a conductive metal layer. A distance from a surface of the conductive metal layer away from the substrate to the substrate is less than or equal to a distance from a surface of the insulating layer away from the substrate to the substrate.
    Type: Application
    Filed: April 14, 2021
    Publication date: September 15, 2022
    Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yanyong SONG, Yanfeng LI, Haoyi XIN, Xu QIAO, Chenrong QIAO, Wei REN, Yu XING, Jingjing XU, Rula SHA, Guolei ZHI, Guangshuai WANG, Liwen XIN, Jingwei HOU
  • Publication number: 20220120511
    Abstract: A heat pipe structure and a manufacturing method are provided. The heat pipe structure includes a case, a wick structure and two lateral sealing structures. The case includes an enclosed space in a sealing state. The wick structure is disposed within the enclosed space and includes a first end and a second end opposite to each other. The two lateral sealing structures are configured to seal two opposite sides of the case. One of the two lateral sealing structures clamps the first end of the wick structure. The other of the lateral sealing structures clamps the second end of the wick structure.
    Type: Application
    Filed: June 1, 2021
    Publication date: April 21, 2022
    Inventors: Shih-Lin Huang, Xiaojun Chen, Guangshuai Wang
  • Patent number: 11099673
    Abstract: Disclosed is a touch display panel, a display device and a method for manufacturing a touch display panel. The touch display panel includes a ground wire and a switching element. The ground wire is configured to allow static electricity in the touch display panel to be discharged through the ground wire. The switching element is configured to be turned on or turned off according to an operating state of the touch display panel to control whether the static electricity is discharged through the ground wire.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: August 24, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jingyi Xu, Yuelin Wang, Guangshuai Wang, Yanwei Ren, Peirong Huo, Xintong Fan, Jinyu Chao
  • Patent number: 10977970
    Abstract: The disclosure provides an array substrate, a display device, a detecting apparatus and a detecting method for detecting a defect connection of a data line. A data signal input bus of the array substrate of the present disclosure applies a data signal to each pixel unit, and a detection line is added on one side of the array substrate opposite to the data signal input bus, when the product is detected, the data signal input bus inputs the normal data signal, the detection line on the other side inputs a signal having a polarity contrary to that of the data signal. At a position of the data line existing defect connection, heat is generated and the data line is burnt at the position existing defect connection.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 13, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Wei Zhang, Yezhou Fang, Le Sun, Wenlong Zhang, Guangshuai Wang
  • Publication number: 20200272267
    Abstract: Disclosed is a touch display panel, a display device and a method for manufacturing a touch display panel. The touch display panel includes a ground wire and a switching element. The ground wire is configured to allow static electricity in the touch display panel to be discharged through the ground wire. The switching element is configured to be turned on or turned off according to an operating state of the touch display panel to control whether the static electricity is discharged through the ground wire.
    Type: Application
    Filed: March 12, 2019
    Publication date: August 27, 2020
    Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jingyi XU, Yuelin WANG, Guangshuai WANG, Yanwei REN, Peirong HUO, Xintong FAN, Jinyu CHAO
  • Patent number: 10636783
    Abstract: An array substrate assembly, a method of manufacturing the array substrate assembly, a display panel and a display apparatus are disclosed. The array substrate assembly includes a drive control circuit located on the substrate and configured for driving. The drive control circuit includes a plurality of thin film transistors each including an active layer. The array substrate further includes a grounded electrostatic shield layer. The electrostatic shield layer is located between the substrate and the drive control circuit, and an orthogonal projection of the electrostatic shield layer on the substrate covers orthogonal projections of at least the active layers of the plurality of thin film transistors of the drive control circuit on the substrate.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: April 28, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Liwen Xin, Wei Zhang, Yanshun Hao, Yezhou Fang, Guangshuai Wang
  • Publication number: 20190130804
    Abstract: The disclosure provides an array substrate, a display device, a detecting apparatus and a detecting method for detecting a defect connection of a data line. A data signal input bus of the array substrate of the present disclosure applies a data signal to each pixel unit, and a detection line is added on one side of the array substrate opposite to the data signal input bus, when the product is detected, the data signal input bus inputs the normal data signal, the detection line on the other side inputs a signal having a polarity contrary to that of the data signal. At a position of the data line existing defect connection, heat is generated and the data line is burnt at the position existing defect connection.
    Type: Application
    Filed: October 25, 2018
    Publication date: May 2, 2019
    Inventors: Wei ZHANG, Yezhou FANG, Le SUN, Wenlong ZHANG, Guangshuai WANG
  • Publication number: 20190131295
    Abstract: An array substrate assembly, a method of manufacturing the array substrate assembly, a display panel and a display apparatus are disclosed. The array substrate assembly includes a drive control circuit located on the substrate and configured for driving. The drive control circuit includes a plurality of thin film transistors each including an active layer. The array substrate further includes a grounded electrostatic shield layer. The electrostatic shield layer is located between the substrate and the drive control circuit, and an orthogonal projection of the electrostatic shield layer on the substrate covers orthogonal projections of at least the active layers of the plurality of thin film transistors of the drive control circuit on the substrate.
    Type: Application
    Filed: May 11, 2018
    Publication date: May 2, 2019
    Inventors: Liwen Xin, Wei Zhang, Yanshun Hao, Yezhou Fang, Guangshuai Wang