Abstract: An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

Abstract: A device comprises a receiver configured to receive a join-lookup remote procedural call (RPC) for a file, wherein the join-lookup RPC requests a join operation of sub-files associated with the file, and a transmitter configured to transmit the file in response to the Join-Lookup RPC. A distributed file system (DFS) client comprises a transmitter configured to transmit a join-lookup RPC for a file, wherein the join-lookup RPC requests a join operation of sub-files associated with the file, and a receiver configured to receive the file in response to the Join-Lookup RPC. A method comprises receiving a join-lookup RPC for a file, wherein the join-lookup RPC requests a join operation of sub-files associated with the file, and transmitting the file in response to the Join-Lookup RPC.

Abstract: A method implemented by a network element (NE) in a network, comprising composing a first network storage entity by mapping a plurality of logical storage units to a plurality of physical storage units in a physical storage system according to a first storage metric associated with the plurality of physical storage units, arranging the plurality of logical storage units sequentially to form a logical circular buffer, and designating a current logical storage unit for writing data and an upcoming logical storage unit for writing data after the current storage unit is fully written, and rebalancing the physical storage system while the physical storage system is actively performing network storage operations by relocating at least one of the logical storage units to a different physical storage unit according to a second storage metric associated with the plurality of physical storage units.

Abstract: An approach to offloading probabilistic computations is described. An application server comprising a memory and a processor and coupled to a network-attached storage device configured to create a dedicated process in response to a procedural call to a virtual machine container based on a data request is disclosed. The processor forwards the data request to the network-attached storage device, programs one or more virtual machines to perform a probabilistic computation based on the procedural call, and directs the probabilistic computation to a first virtual machine of the one or more virtual machines. The request for data is transformed into a modified call using a virtualized lookup call.

Abstract: An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

Abstract: Embodiments of the present invention provide a data processing system and a data processing method. An MMIO address of a data request is obtained, where data stored in a PCIe storage device can be directly obtained from the MMIO address, and according to the MMIO address, a network adapter can directly read the data from the PCIe storage device of the data processing system, and transmit the data to a second data processing system, or directly write the data received from the second data processing system into the PCIe storage device. Therefore, the processing system can implement transmitting data directly from the PCIe storage device to the network adapter without using memory. During data transmission between the two data processing systems, a usage ratio of a resource, such as memory and a CPU, is reduced, and efficiency of data transmission is improved.

Abstract: A peripheral component interconnect express PCI-e network system having a processor for (a) assigning addresses to the PCI-e topology tree, comprising: traversing, at a given level and in a breadth direction, down-link couplings to an interconnection; ascertaining, at the level, which of the down-link couplings are connected to nodes; assigning, at the level, addresses to nodes of ascertained down-link coupling having nodes; and (b) propagating, a level, comprising: traversing, at the level and in a depth direction, down-link couplings to the interconnection of the PCI-e network, ascertaining, at the level, which of the downlink couplings are coupled to other interconnections in the depth direction, consecutively proceeding in the depth direction, to a next level of the down-link coupling of a next interconnection; and alternatively repeating (a) and (b) until the nodes are assigned addresses within the PCI-e tree topology network.

Abstract: Embodiments of the present invention disclose a cooperative caching method and apparatus, relating to the field of network technologies, to improve the local hit ratio without increasing the local server costs. The technical solution provided in the present invention includes: obtaining, according to cache information, end-to-end delay between a local server and a neighbor server, and popularity in a cache list, a consolidated gain value of a cached video segment and a consolidated gain value of a candidate video segment in the local server; and replacing the cached video segment with the candidate video segment when the consolidated gain value of the cached video segment and the consolidated gain value of the candidate video segment in the local server meet a replacement condition.

Abstract: In a high-dimensional PCI-Express (PCIe) network, implementation of alternative paths is accomplished to facilitate flexible topology implementation and network domain scaling while enabling improved communication latency. Different portions of the PCIe tree structure are connected to allow a shorter path for communications by utilizing a bridge circuit configured as an end-point with respect to two switches that are not directly connected in the PCIe tree topology. The bridge circuit performs address translations to allow communications from one switch to be passed via the bridge circuit to the other switch.

Abstract: An instruction from an application server to perform a computation is received at a network-attached storage (NAS) device. The computation uses arrays of data that are stored by the NAS device as inputs. The instruction includes remote procedure calls that identify operations that are included in the computation, including a first remote procedure call that will cause the NAS device to perform a read operation on a first file containing an array of data to be used as an input for the computation, and a second remote procedure call that will cause the NAS device to perform an array operation using the array of data. The operations are executed on the NAS device to produce a result that is stored in a second file in a location in a file system managed by the NAS device and accessible to the application server.

Abstract: A method comprising receiving a plurality of data records, storing the data records as data segments in a storage element, receiving a plurality of descriptors for each data segment, wherein each descriptor describes an aspect of data contained in the data segments, employing a first user-defined function to resolve a first minimum descriptor for each data segment and a first maximum descriptor for each data segment, composing a lightweight index for the data segments, wherein the lightweight index comprises the first minimum descriptor for each data segment and the first maximum descriptor for each data segment, and appending the lightweight index to the data segments in the storage element.

Abstract: An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

Abstract: Systems and methods for offloading computations from a CPU directly to an accelerator engine are disclosed. One embodiment includes determining a function of an application to be offloaded from a CPU to an accelerator engine, locating data within a file necessary to perform the functions, programming a logic of the accelerator engine based on the function to be offloaded, programming a DMA engine to move a copy the data from a secondary storage device to the accelerator engine, and processing the data at the accelerator engine using the programmed logic.

Abstract: Embodiments of the present invention provide a data processing system and a data processing method. An MMIO address of a data request is obtained, where data stored in a PCIe storage device can be directly obtained from the MMIO address, and according to the MMIO address, a network adapter can directly read the data from the PCIe storage device of the data processing system, and transmit the data to a second data processing system, or directly write the data received from the second data processing system into the PCIe storage device. Therefore, the processing system can implement transmitting data directly from the PCIe storage device to the network adapter without using memory. During data transmission between the two data processing systems, a usage ratio of a resource, such as memory and a CPU, is reduced, and efficiency of data transmission is improved.

Abstract: A pre-processing method and system for cooperative communication are provided. The method includes: after obtaining channel matrices collected by a Base Station (BS), obtaining Multiple-Input Multiple-Output (MIMO) Cooperation Area (CA) information, in which the MIMO CA information includes cooperation information between BSs, and the cooperation information between the BSs is used to determine an interference relation between MIMO CAs; combining the channel matrices of a User Equipment (UE) according to the interference relation between the MIMO CAs; and performing pre-coding computation of the UE by using the combined channel matrices.

Abstract: The descriptions presented herein include explanation of high-dimensional PCI-Express (PCIe) network implementations. The new approaches can facilitate utilization of an efficient protocol (e.g., PCIe, etc.) while enabling implementation of various characteristics and features (e.g., characteristics and features similar to a fat-tree topology, CLOS topology, 2D and 3D topologies, etc.) that would otherwise not be compatible with the protocol. For example, implementation of alternative paths can be enabled and utilized while maintaining compliance with a protocol (e.g., PCIe, etc.) that would otherwise not be compatible with the use of alternative paths. The alternative paths can facilitate flexible topology implementation and network domain scaling while enabling improved communication latency.

Abstract: An apparatus is configured to perform a method for a graph based computation. The method includes receiving a procedural call from an application server, the procedural call comprising at least one primitive extended from a distributed file system (DFS) protocol. The method also includes initiating at least one virtual machine. The method further includes performing a graph based computation based on the procedural call using the at least one virtual machine. The method still further includes transmitting a result of the graph based computation to the application server.

Abstract: A method implemented in a memory device, wherein the memory device comprises a first memory and a second memory, the method comprising receiving a direct memory access (DMA) write request from a first central processing unit (CPU) in a first computing system, wherein the DMA write request is for a plurality of bytes of data, in response to the DMA write request receiving the plurality of bytes of data from a memory in the first computing system without processing by the first CPU, and storing the plurality of bytes of data in the first memory, and upon completion of the storing, sending an interrupt message to a second CPU in a second computing system, wherein the interrupt message is configured to interrupt processing of the second CPU and initiate transfer of the plurality of bytes of data to a memory in the second computing system.

Abstract: The descriptions presented herein include explanation of high-dimensional PCI-Express (PCIe) network implementations. The new approaches can facilitate utilization of an efficient protocol (e.g., PCIe, etc.) while enabling implementation of various characteristics and features (e.g., characteristics and features similar to a fat-tree topology, CLOS topology, 2D and 3D topologies, etc.) that would otherwise not be compatible with the protocol. For example, implementation of alternative paths can be enabled and utilized while maintaining compliance with a protocol (e.g., PCIe, etc.) that would otherwise not be compatible with the use of alternative paths. The alternative paths can facilitate flexible topology implementation and network domain scaling while enabling improved communication latency.

Abstract: Embodiments of the present invention provide a data processing system and a data processing method. An MMIO address of a data request is obtained, where data stored in a PCIe storage device can be directly obtained from the MMIO address, and according to the MMIO address, a network adapter can directly read the data from the PCIe storage device of the data processing system, and transmit the data to a second data processing system, or directly write the data received from the second data processing system into the PCIe storage device. Therefore, the processing system can implement transmitting data directly from the PCIe storage device to the network adapter without using memory. During data transmission between the two data processing systems, a usage ratio of a resource, such as memory and a CPU, is reduced, and efficiency of data transmission is improved.