Patents by Inventor Guillaume Boccardi
Guillaume Boccardi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230395561Abstract: The present disclosure relates to at least one multilayer structure that is produced on a semiconductor donor wafer, by growing e.g. group III-V material in a cavity formed in a dielectric support layer. A template layer embeds the multilayer structure. The multilayer structure comprises a release layer that is accessible from the sides. The method further comprises the production of a device and the production of conductive paths connected to the device and terminating in a number of contact pads which are coplanar with a first dielectric bonding surface. The donor wafer is then bonded to a carrier wafer. TSV openings are then produced from the back side of the carrier wafer and an etchant is provided for selectively removing layers of the multilayer structure. The etchant is supplied through the TSV openings for the removal of the release layer. The donor wafer is thereby released to form separate semiconductor chips.Type: ApplicationFiled: June 2, 2023Publication date: December 7, 2023Inventors: Abhitosh Vais, Bertrand Paravais, Guillaume Boccardi, Bernardette Kunert, Yves Mols, Sachin Yadav
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Patent number: 10872824Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.Type: GrantFiled: February 20, 2019Date of Patent: December 22, 2020Assignee: IMEC VZWInventors: Clement Merckling, Guillaume Boccardi
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Publication number: 20190181050Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.Type: ApplicationFiled: February 20, 2019Publication date: June 13, 2019Inventors: Clement Merckling, Guillaume Boccardi
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Patent number: 10256157Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.Type: GrantFiled: November 29, 2017Date of Patent: April 9, 2019Assignee: IMEC VZWInventors: Clement Merckling, Guillaume Boccardi
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Patent number: 9947591Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.Type: GrantFiled: November 16, 2016Date of Patent: April 17, 2018Assignee: IMEC VZWInventors: Clement Merckling, Guillaume Boccardi
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Publication number: 20180082907Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.Type: ApplicationFiled: November 29, 2017Publication date: March 22, 2018Applicant: IMEC VZWInventors: Clement Merckling, Guillaume Boccardi
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Publication number: 20170178971Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.Type: ApplicationFiled: November 16, 2016Publication date: June 22, 2017Applicant: IMEC VZWInventors: Clement Merckling, Guillaume Boccardi
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Patent number: 9105746Abstract: A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures.Type: GrantFiled: October 22, 2014Date of Patent: August 11, 2015Assignee: IMEC VZWInventors: Min-Soo Kim, Guillaume Boccardi, Soon Aik Chew, Naoto Horiguchi
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Patent number: 9041149Abstract: The invention relates to a semiconductor device (30) comprising a substrate (1), a semiconductor body (25) comprising a bipolar transistor that comprises a collector region (3), a base region (4), and an emitter region (15), wherein at least a portion of the collector region (3) is surrounded by a first isolation region (2, 8), the semiconductor body (25) further comprises an extrinsic base region (35) arranged in contacting manner to the base region (4). In this way, a fast semiconductor device with reduced impact of parasitic components is obtained.Type: GrantFiled: August 5, 2009Date of Patent: May 26, 2015Assignee: NXP, B.V.Inventors: Guillaume Boccardi, Mark C. J. C. M. Kramer, Johannes J. T. M. Donkers, Li Jen Choi, Stefaan Decoutere, Arturo Sibaja-Hernandez, Stefaan Van Huylenbroeck, Rafael Venegas
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Publication number: 20150111351Abstract: A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures.Type: ApplicationFiled: October 22, 2014Publication date: April 23, 2015Applicant: IMEC VZWInventors: Min-Soo Kim, Guillaume Boccardi, Soon Aik Chew, Naoto Horiguchi
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Patent number: 8963219Abstract: A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source.Type: GrantFiled: October 11, 2011Date of Patent: February 24, 2015Assignee: NXP B.V.Inventors: Gilberto Curatola, Dusan Golubovic, Johannes Josephus Theodorus Marinus Donkers, Guillaume Boccardi, Hans Mertens
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Patent number: 8716812Abstract: A field effect transistor having a gate structure comprising a high-K dielectric layer, a gate electrode located on the high-K dielectric layer, and an interfacial layer located in between the high-K dielectric layer and a channel region of the field effect transistor. The interfacial layer comprises a layer of SiO2 containing a regrowth inhibiting agent. A method of forming the gate structure includes forming a gate stack comprising, in order: a SiO2 layer adjacent a channel region of the field effect transistor; a high-K dielectric layer on the SiO2 layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing a regrowth inhibiting agent into the SiO2 layer and then annealing the gate structure. The presence of the regrowth inhibiting agent in the SiO2 interfacial layer inhibits regrowth of the SiO2 layer into the channel region during the annealing step.Type: GrantFiled: June 24, 2009Date of Patent: May 6, 2014Assignee: NXP B.V.Inventors: Markus Mueller, Guillaume Boccardi, Jasmine Petry
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Patent number: 8541812Abstract: A semiconductor device (10) comprising a bipolar transistor and a field effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22d and 22e) and a base region (33d) of the bipolar transistor. The bipolar transistor is provided with a first insulating cavity (92) provided in the collector region (22d and 22e). The base region (33d) is narrower in the plane of the substrate than the collector region (22d and 22e) due to a second insulating cavity (94) provided around the base region (33d) and between the collector region (22d and 22e) and the emitter region (4). By blocking diffusion from the base region the first insulating cavity (92) provides a reduction in the base collector capacitance and can be described as defining the base contact.Type: GrantFiled: February 26, 2009Date of Patent: September 24, 2013Assignee: NXP B.V.Inventors: Philippe Meunier-Beillard, Mark C. J. C. M. Kramer, Johannes J. T. M. Donkers, Guillaume Boccardi
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Patent number: 8518783Abstract: A field effect transistor having a gate structure that comprises an interfacial layer positioned in between the transistor channel region and a high-K dielectric layer of the gate stack. The interfacial layer comprises AlxSiyOz, which has a higher relative dielectric constant value than SiO2. A method of forming the gate structure of a field effect transistor. The method includes forming a gate stack comprising, in order: a SiO2-based layer adjacent a channel region of the field effect transistor; a high-K dielectric layer on the SiO2-based layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing Al into the SiO2-based layer to form an AlxSiyOz interfacial layer in between the high-K dielectric layer and the channel region. A heating step to allows Al introduced into channel region to diffuse out of the channel region into the interfacial layer.Type: GrantFiled: April 27, 2009Date of Patent: August 27, 2013Assignee: NXP B.V.Inventors: Markus Mueller, Guillaume Boccardi, Jasmine Petry
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Publication number: 20130187241Abstract: A field effect transistor having a gate structure comprising a high-K dielectric layer, a gate electrode located on the high-K dielectric layer, and an interfacial layer located in between the high-K dielectric layer and a channel region of the field effect transistor. The interfacial layer comprises a layer of SiO2 containing a regrowth inhibiting agent. A method of forming the gate structure includes forming a gate stack comprising, in order: a SiO2 layer adjacent a channel region of the field effect transistor; a high-K dielectric layer on the SiO2 layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing a regrowth inhibiting agent into the SiO2 layer and then annealing the gate structure. The presence of the regrowth inhibiting agent in the SiO2 interfacial layer inhibits regrowth of the SiO2 layer into the channel region during the annealing step.Type: ApplicationFiled: June 24, 2009Publication date: July 25, 2013Applicant: NXP B.V.Inventors: Markus Mueller, Guillaume Boccardi, Jasmine Petry
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Publication number: 20120086058Abstract: A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source.Type: ApplicationFiled: October 11, 2011Publication date: April 12, 2012Applicant: NXP B.V.Inventors: Gilberto Curatola, Dusan Golubovic, Johannes Josephus Theodorus Marinus Donkers, Guillaume Boccardi, Hans Mertens
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Publication number: 20120024700Abstract: Disclosed is a sensor device (10) comprising a substrate (100) carrying a sensing element (110), and a metallization stack on said substrate for providing interconnections to said sensing element, the metallization stack comprising a plurality of patterned metal layers (130a-d) separated by insulating layers (120a-d), wherein a first metal layer (130c) comprises an electrode portion (16) conductively connected to the sensing element, and a further metal layer (130d) facing the first metal layer comprises a reference electrode portion (18), the electrode portion and the reference electrode portion being separated by a fluid channel (14) accessible from the top of the metallization stack. A method of manufacturing such a sensor device is also disclosed.Type: ApplicationFiled: July 26, 2011Publication date: February 2, 2012Applicant: NXP B.V.Inventors: Guillaume Boccardi, Magali Huguette Alice Lambert
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Publication number: 20110215417Abstract: A semiconductor device (10) comprising a bipolar transistor and a field effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22d and 22e) and a base region (33d) of the bipolar transistor. The bipolar transistor is provided with a first insulating cavity (92) provided in the collector region (22d and 22e). The base region (33d) is narrower in the plane of the substrate than the collector region (22d and 22e) due to a second insulating cavity (94) provided around the base region (33d) and between the collector region (22d and 22e) and the emitter region (4). By blocking diffusion from the base region the first insulating cavity (92) provides a reduction in the base collector capacitance and can be described as defining the base contact.Type: ApplicationFiled: February 26, 2009Publication date: September 8, 2011Applicant: NXP B.V.Inventors: Philippe Meunier-Beillard, Mark C.J.C.M. Kramer, Johannes J.T.M. Donkers, Guillaume Boccardi
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Publication number: 20110198671Abstract: The invention relates to a semiconductor device (30) comprising a substrate (1), a semiconductor body (25) comprising a bipolar transistor that comprises a collector region (3), a base region (4), and an emitter region (15), wherein at least a portion of the collector region (3) is surrounded by a first isolation region (2, 8), the semiconductor body (25) further comprises an extrinsic base region (35) arranged in contacting manner to the base region (4). In this way, a fast semiconductor device with reduced impact of parasitic components is obtained.Type: ApplicationFiled: August 5, 2009Publication date: August 18, 2011Applicants: NXP B.V., INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZWInventors: Guillaume Boccardi, Mark C. J. C. M. Kramer, Johannes J. T. M. Donkers, Li Jen Choi, Stefaan Decoutere, Arturo Sibaja-Hernandez, Stefaan Van Huylenbroeck, Rafael Venegas
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Publication number: 20110037131Abstract: A field effect transistor having a gate structure that comprises an interfacial layer positioned in between the transistor channel region and a high-K dielectric layer of the gate stack. The interfacial layer comprises AlxSiyOz, which has a higher relative dielectric constant value than SiO2. A method of forming the gate structure of a field effect transistor. The method includes forming a gate stack comprising, in order: a SiO2-based layer adjacent a channel region of the field effect transistor; a high-K dielectric layer on the SiO2-based layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing Al into the SiO2-based layer to form an AlxSiyOz interfacial layer in between the high-K dielectric layer and the channel region. A heating step to allows Al introduced into channel region to diffuse out of the channel region into the interfacial layer.Type: ApplicationFiled: April 27, 2009Publication date: February 17, 2011Applicant: NXP B.V.Inventors: Markus Mueller, Guillaume Boccardi, Jasmine Petry