Patents by Inventor Guillermo J. Rozas

Guillermo J. Rozas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200045134
    Abstract: A method for performing a write operation in a distributed storage system is disclosed. The method comprises receiving a first time-stamped write request from a proxy server. Further, the method comprises determining if the first time-stamped write request is within a time window of a reorder buffer and if the first time-stamped write request overlaps with a second time-stamped write request in the reorder buffer. Responsive to a determination that the first time-stamped write request is outside the time window or that the first time-stamped write request is within the time window but has an older time-stamp than the second time-stamped write request, the method comprises rejecting the first time-stamped write request. Otherwise, the method comprises inserting the first time-stamped write request in the reorder buffer in timestamp order and transmitting an accept to the proxy server.
    Type: Application
    Filed: August 6, 2018
    Publication date: February 6, 2020
    Inventor: Guillermo J. ROZAS
  • Publication number: 20200042199
    Abstract: A method for performing a write operation in a distributed storage system is disclosed. The method comprises receiving a first time-stamped write request from a proxy server. Further, the method comprises determining if the first time-stamped write request is within a time window of a reorder buffer and if the first time-stamped write request overlaps with a second time-stamped write request in the reorder buffer. Responsive to a determination that the first time-stamped write request is outside the time window or that the first time-stamped write request is within the time window but has an older time-stamp than the second time-stamped write request, the method comprises rejecting the first time-stamped write request. Otherwise, the method comprises inserting the first time-stamped write request in the reorder buffer in timestamp order and transmitting an accept to the proxy server.
    Type: Application
    Filed: August 6, 2018
    Publication date: February 6, 2020
    Inventor: Guillermo J. ROZAS
  • Patent number: 10540283
    Abstract: A coherence decoupling buffer. In accordance with a first embodiment, a coherence decoupling buffer is for storing tag information of cache lines evicted from a plurality of cache memories. A coherence decoupling buffer may be free of value information of the plurality of cache memories. A coherence decoupling buffer may also be combined with a coherence memory.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: January 21, 2020
    Assignee: Facebook, Inc.
    Inventor: Guillermo J. Rozas
  • Patent number: 10234893
    Abstract: A dual-domain dynamic multiplexer and a method of transitioning between asynchronous voltage and frequency domains. One embodiment of the dual-domain dynamic multiplexer includes: (1) a first domain having a first voltage and a first clock, and a second domain having a second voltage and a second clock, (2) a plurality of data and data select input pairs wherein a data input of an input pair is in the first domain and a data select input of an input pair is in the second domain, and (3) a pre-charge stage in the second domain that is energized upon an edge of the second clock, whereby one data and data input pair is enabled and data latched in the second domain upon another edge of the second clock.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: March 19, 2019
    Assignee: Nvidia Corporation
    Inventors: Guillermo J Rozas, Jason Golbus, Chi Keung Lee
  • Patent number: 10108424
    Abstract: The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 23, 2018
    Assignee: Nvidia Corporation
    Inventors: Nathan Tuck, Alexander Klaiber, Ross Segelken, David Dunn, Ben Hertzberg, Rupert Brauch, Thomas Kistler, Guillermo J. Rozas, Madhu Swarna
  • Patent number: 10102142
    Abstract: A method for detecting an instruction ordering violation in a CPU. The method includes receiving a reordered stream of instructions and detecting whether an ordering violation has occurred by using virtual addresses. The method further includes transferring results of the reordered stream of instructions from a load store buffer into a cache and detecting whether an ordering violation has occurred by using physical addresses. Subsequently, a recovery is initiated upon detection of an ordering violation.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: October 16, 2018
    Assignee: Nvidia Corporation
    Inventors: Guillermo J. Rozas, Bharath Krishnan, James Van Zoeren
  • Patent number: 9891972
    Abstract: Embodiments related to managing lazy runahead operations at a microprocessor are disclosed. For example, an embodiment of a method for operating a microprocessor described herein includes identifying a primary condition that triggers an unresolved state of the microprocessor. The example method also includes identifying a forcing condition that compels resolution of the unresolved state. The example method also includes, in response to identification of the forcing condition, causing the microprocessor to enter a runahead mode.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: February 13, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Magnus Ekman, Ross Segelken, Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt, Sridharan Ramakrishnan, Hens Vanderschoot, Darrell D. Boggs
  • Patent number: 9875105
    Abstract: Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: January 23, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Guillermo J. Rozas, Paul Serris, Brad Hoyt, Sridharan Ramakrishnan, Hens Vanderschoot, Ross Segelken, Darrell Boggs, Magnus Ekman
  • Patent number: 9823931
    Abstract: Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes identifying a runahead-triggering event associated with a runahead-triggering instruction and, responsive to identification of the runahead-triggering event, entering runahead operation and inserting the runahead-triggering instruction along with one or more additional instructions in a queue. The example method also includes resuming non-runahead operation of the microprocessor in response to resolution of the runahead-triggering event and re-dispatching the runahead-triggering instruction along with the one or more additional instructions from the queue to the execution logic.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 21, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt, Sridharan Ramakrishnan, Hens Vanderschoot, Ross Segelken, Darrell D. Boggs, Magnus Ekman, Aravindh Baktha, David Dunn
  • Patent number: 9740553
    Abstract: Embodiments related to managing potentially invalid results generated/obtained by a microprocessor during runahead are provided. In one example, a method for operating a microprocessor includes causing the microprocessor to enter runahead upon detection of a runahead event. The example method also includes, during runahead, determining that an operation associated with an instruction referencing a storage location would produce a potentially invalid result based on a value of an architectural poison bit associated with the storage location and performing a different operation in response.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: August 22, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Bruce Holmer, Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt, Sridharan Ramakrishnan, Hens Vanderschoot, Ross Segelken, Darrell D. Boggs, Magnus Ekman
  • Publication number: 20170199778
    Abstract: Embodiments related to managing lazy runahead operations at a microprocessor are disclosed. For example, an embodiment of a method for operating a microprocessor described herein includes identifying a primary condition that triggers an unresolved state of the microprocessor. The example method also includes identifying a forcing condition that compels resolution of the unresolved state. The example method also includes, in response to identification of the forcing condition, causing the microprocessor to enter a runahead mode.
    Type: Application
    Filed: March 27, 2017
    Publication date: July 13, 2017
    Inventors: Magnus Ekman, Ross Segelken, Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt, Sridharan Ramakrishnan, Hens Vanderschoot, Darrell D. Boggs
  • Patent number: 9645929
    Abstract: In a processor, a method for speculative permission acquisition for access to a shared memory. The method includes receiving a store from a processor core to modify a shared cache line, and in response to receiving the store, marking the cache line as speculative. The cache line is then modified in accordance with the store. Upon receiving a modification permission, the modified cache line is subsequently committed.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 9, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: James Van Zoeren, Alexander Klaiber, Guillermo J. Rozas, Paul Serris
  • Publication number: 20170116126
    Abstract: A coherence decoupling buffer. In accordance with a first embodiment, a coherence decoupling buffer is for storing tag information of cache lines evicted from a plurality of cache memories. A coherence decoupling buffer may be free of value information of the plurality of cache memories. A coherence decoupling buffer may also be combined with a coherence memory.
    Type: Application
    Filed: January 6, 2017
    Publication date: April 27, 2017
    Inventor: Guillermo J. Rozas
  • Patent number: 9632976
    Abstract: Embodiments related to managing lazy runahead operations at a microprocessor are disclosed. For example, an embodiment of a method for operating a microprocessor described herein includes identifying a primary condition that triggers an unresolved state of the microprocessor. The example method also includes identifying a forcing condition that compels resolution of the unresolved state. The example method also includes, in response to identification of the forcing condition, causing the microprocessor to enter a runahead mode.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 25, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt, Sridharan Ramakrishnan, Hens Vanderschoot, Ross Segelken, Darrell D. Boggs, Magnus Ekman
  • Patent number: 9569214
    Abstract: In one embodiment, in an execution pipeline having a plurality of execution subunits, a method of using a bypass network to directly forward data from a producing execution subunit to a consuming execution subunit is provided. The method includes producing output data with the producing execution subunit, consuming input data with the consuming execution subunit, for one or more intervening operations whose input is the output data from the producing execution subunit and whose output is the input data to the consuming execution subunit, evaluating those one or more intervening operations to determine whether their execution would compose an identify function, and if the one or more intervening operations would compose such an identity function, controlling the bypass network to forward the producing execution subunit's output data directly to the consuming execution subunit.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: February 14, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Gokul Govindu, Parag Gupta, Scott Pitkethly, Guillermo J. Rozas
  • Patent number: 9558116
    Abstract: A coherence decoupling buffer. In accordance with a first embodiment, a coherence decoupling buffer is for storing tag information of cache lines evicted from a plurality of cache memories. A coherence decoupling buffer may be free of value information of the plurality of cache memories. A coherence decoupling buffer may also be combined with a coherence memory.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: January 31, 2017
    Assignee: Intellectual Ventures Holding 81 LLC
    Inventor: Guillermo J. Rozas
  • Patent number: 9411595
    Abstract: The disclosure provides systems and methods for maintaining cache coherency in a multi-threaded processing environment. For each location in a data cache, a global state is maintained specifying the coherency of the cache location relative to other data caches and/or to a shared memory resource backing the data cache. For each cache location, thread state information associated with a plurality of threads is maintained. The thread state information is specified separately and in addition to the global state, and is used to individually control read and write permissions for each thread for the cache location. The thread state information is also used, for example by a cache controller, to control whether uncommitted transactions of threads relating to the cache location are to be rolled back.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: August 9, 2016
    Assignee: NVIDIA CORPORATION
    Inventor: Guillermo J. Rozas
  • Patent number: 9081563
    Abstract: Apparatus and a method for causing scheduler software to produce code which executes more rapidly by ignoring some of the normal constraints placed on its scheduling operations and simply scheduling certain instructions to run as fast as possible, raising an exception if the scheduling violates a scheduling constraint, and determining steps to be taken for correctly executing each set of instructions about which an exception is raised.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: July 14, 2015
    Inventors: Guillermo J. Rozas, Godfrey P. D'Souza, Charles R. Price, Paul S. Serris
  • Patent number: 8924648
    Abstract: A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: December 30, 2014
    Inventors: H. Peter Anvin, Guillermo J. Rozas, Alexander Klaiber, John P. Banning
  • Patent number: 8898395
    Abstract: Methods and systems for maintaining cache consistency are described. A group of instructions is executed. The group of instructions can include multiple memory operations, and also includes an instruction that when executed causes a cache line to be accessed. In response to execution of that instruction, an indicator associated with the group of instructions is updated to indicate that the cache line has been accessed. The cache line is indicated as having been accessed until execution of the group of instructions is ended.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: November 25, 2014
    Inventor: Guillermo J. Rozas