Abstract: A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.

Abstract: A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.

Abstract: The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.

Abstract: The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.

Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.

Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.

Abstract: A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided.

Abstract: A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided.

Abstract: A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided.

Abstract: A circuit board with a buried conductive trace formed thereon according to the present invention is provided. A buried conductive trace layer is formed on the surface of a substrate and the pads and fingers of the conductive trace layer are heightened to facilitate the subsequent process of molding.

Abstract: A via hole structure and a manufacturing method thereof are provided. The via hole structure is disposed on a substrate. The substrate has a through hole, which passes through the substrate from a top surface to a bottom surface. The via hole structure comprises a conductive layer, several first conductive lines and several second conductive lines. The conductive layer having several conductive sections is disposed on the inner wall of the through hole. The first conductive lines are adjacent to the top surface for connecting the top ends of the conductive sections. The second conductive lines are adjacent to the bottom surface for connecting the bottom ends of the conductive sections. The conductive sections, the first conductive lines and the second conductive lines are serially connected to form a three-dimension layout.

Abstract: A manufacturing method and structure for substrate with vertically embedded capacitors includes the steps of providing a plurality of conductive layers having a first dielectric layer and a leading wire layer formed on the first dielectric layer, providing a plurality of composite layers having a second dielectric layer and a patterned electrode layer formed on the second dielectric layer, laminating the conductive layers and the composite layers to form a block which defines a plurality of substrates with vertically embedded capacitors and a plurality of sawing streets between the substrates, and sawing the block along the sawing streets to singularize the substrates.

Abstract: A substrate for inspecting a thickness of contacts at least includes a dielectric layer, a first metal layer, and a second metal layer. The first metal layer which includes a circuit region and a testing region is formed on an upper surface of the dielectric layer, and the circuit region has a plurality of contacts. The second metal layer which has a hollowed region is formed on a lower surface of the dielectric layer, and the hollowed region is aligned with the testing region of the first metal layer to avoid the interference when the testing region is inspected.

Abstract: A package substrate strip having a reserved plating bar and a metal surface treatment method thereof are provided. The metal surface treatment method forms a conductive layer connecting the reserved plating bar and bonding pads of the package substrate stripe and further forms an isolating layer covering the conductive layer. By original plating bars and the reserved plating bar, an anti-oxidation layer can be simultaneously formed on finger contacts, first ball pads electrically connected to the finger contacts, and second ball pads electrically connected to the bonding pads. The package substrate strip and the method for metal surface treatment thereof can simplify manufacturing process, reduce production cost, and improve production efficiency and yield. Furthermore, a chip package applying the package substrate strip is also provided.

Abstract: A circuit board with a buried conductive trace formed thereon according to the present invention is provided. A buried conductive trace layer is formed on the surface of a substrate and the pads and fingers of the conductive trace layer are heightened to facilitate the subsequent process of molding.

Abstract: A circuit board with a buried conductive trace formed thereon according to the present invention is provided. A buried conductive trace layer is formed on the surface of a substrate and the pads of the conductive trace layer are plated with a layer of copper so that the pads are heightened to facilitate the subsequent process of molding.

Abstract: A substrate for inspecting a thickness of contacts at least includes a dielectric layer, a first metal layer, and a second metal layer. The first metal layer which includes a circuit region and a testing region is formed on an upper surface of the dielectric layer, and the circuit region has a plurality of contacts. The second metal layer which has a hollowed region is formed on a lower surface of the dielectric layer, and the hollowed region is aligned with the testing region of the first metal layer to avoid the interference when the testing region is inspected.

Abstract: A package substrate strip having a reserved plating bar and a metal surface treatment method thereof are provided. The metal surface treatment method forms a conductive layer connecting the reserved plating bar and bonding pads of the package substrate stripe and further forms an isolating layer covering the conductive layer. By original plating bars and the reserved plating bar, an anti-oxidation layer can be simultaneously formed on finger contacts, first ball pads electrically connected to the finger contacts, and second ball pads electrically connected to the bonding pads. The package substrate strip and the method for metal surface treatment thereof can simplify manufacturing process, reduce production cost, and improve production efficiency and yield. Furthermore, a chip package applying the package substrate strip is also provided.

Abstract: A via hole structure and a manufacturing method thereof are provided. The via hole structure is disposed on a substrate. The substrate has a through hole, which passes through the substrate from a top surface to a bottom surface. The via hole structure comprises a conductive layer, several first conductive lines and several second conductive lines. The conductive layer having several conductive sections is disposed on the inner wall of the through hole. The first conductive lines are adjacent to the top surface for connecting the top ends of the conductive sections. The second conductive lines are adjacent to the bottom surface for connecting the bottom ends of the conductive sections. The conductive sections, the first conductive lines and the second conductive lines are serially connected to form a three-dimension layout.

Abstract: A package substrate, including a base layer, a surface circuit layer, a plurality of conductive bumps, and a patterned solder mask layer, is provided. The surface circuit layer having a plurality of bonding pads is disposed on a surface of the base layer. The conductive bumps are disposed on the bonding pads individually. The patterned solder mask layer is disposed on the surface of the base layer and outside a corresponding region occupied by the conductive bumps, so as to expose the conductive bumps. In addition, a method of fabricating the package substrate and a chip package structure employing the package substrate are also provided.