Abstract: Methods and apparatus for supplying power to a dynamic load, such as a neural network circuit. One example power supply circuit generally includes a voltage regulator circuit and a distribution circuit coupled to one or more outputs of the voltage regulator circuit. The distribution circuit is configured to output different amounts of current based on changes in the dynamic load. For certain aspects, the dynamic load includes a neural network circuit having a plurality of segments. In this case, the distribution circuit may be configured to output the different amounts of current based on which segment in the plurality of segments of the neural network circuit is active.

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line.

Abstract: Certain aspects of the present disclosure are directed to an apparatus for voltage regulation. The apparatus generally includes a first switch, an inductive element, the first switch being coupled between a first voltage rail and a first terminal of the inductive element, a second switch coupled between a second voltage rail and the first terminal of the inductive element, a third switch coupled between a second terminal of the inductive element and a reference potential node, and a fourth switch coupled between the second terminal of the inductive element and an output node.

Abstract: A compute-in-memory array is provided in which each neuron includes a capacitor and an output transistor. During an evaluation phase, a filter weight voltage and the binary state of an input bit controls whether the output transistor conducts or is switched off to affect a voltage of a read bit line connected to the output transistor.

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line.

Abstract: A system and method of improving the efficiency in the power consumption of an audio system. In essence, the technique is to adjust the power delivered from the power supply to the analog section, such as the power amplifier, in response to the volume level indicated by the volume control module and/or in response to the detected characteristic of the input audio signal. Thus, in this manner, the analog section is operated in a manner that is related to the level of the signal it is processing. Additionally, the system and method also relate to a technique of adjusting the dynamic ranges of the digital signal and the analog signal to improve the overall dynamic range of the system without needing to consume additional power.

Abstract: A headset in-use detector is disclosed. In an exemplary embodiment, an apparatus includes a detector configured to receive a sound signal and an echo signal and generate a detection signal, and a controller configured to determine whether or not a headset is in-use based on the detection signal.

Abstract: Techniques for sensing the resistance of a load. In an aspect, a sense resistor is provided in series with the load. Each terminal of the sense resistor is alternately coupled via switches to a sense amplifier. A second input of the sense resistor is coupled to a terminal of the load. The voltage drop across the load and the voltage drop across the load plus sense resistor are alternatively measured. These voltage drops may be digitized and used to compute a resistance of the load using, e.g., a digital processor.

Abstract: An audio system that reduces or eliminates click and pop noise during power up and power down operations. In particular, the audio system includes an amplifier with an input adapted to receive an input audio signal and an output adapted to produce an amplified output audio signal for an associated speaker. The audio system further includes a noise reduction circuit adapted to smoothly apply and remove a DC voltage to and from the output of the amplifier in a manner that reduces or eliminates click and pop noise from being generated by the associated speaker. The DC voltage at the output of the amplifier may be derived from a DC reference voltage source and/or from the input audio signal.

Abstract: Techniques for utilizing a plurality of switches to reduce crosstalk in a headset jack for accommodating both European and North American type headset plugs. In an aspect, a six-switch solution is provided to selectively couple first and second terminals of the jack to a ground and a microphone terminal, and further to selectively couple a ground sensing input to the first or second terminal of the jack. The ground sensing input is provided to left and right audio channel amplifiers for driving the corresponding left and right terminals of the headset, to provide a common-mode reference level to the left and right audio channel amplifiers. In another aspect, at least four physical pins are provided to couple the switches to the ground and microphone terminals of the jack, and the connections between the ground sensing inputs and the jack may be provided adjacent to the jack for better isolation.

Abstract: Techniques for designing a transconductor configurable to have a low transconductance. In one aspect, a voltage to current conversion module is coupled to a 1:N current replication module. The voltage to current conversion module may be implemented as an operational amplifier configured with negative feedback to generate a current through a transistor, wherein such current is proportional to the difference between an input voltage and a common-mode reference. The 1:N current replication module is configured to mirror the generated current in another transistor, to a predetermined ratio, such that the output current is also proportional to the difference between the input voltage and the common-mode reference. In exemplary embodiments, the output stage driving the output current may be configured to operate as a Class A, Class B, or Class AB type amplifier.

Abstract: Techniques for sensing the resistance of a load. In an aspect, a sense resistor is provided in series with the load. Each terminal of the sense resistor is alternately coupled via switches to a sense amplifier. A second input of the sense resistor is coupled to a terminal of the load. The voltage drop across the load and the voltage drop across the load plus sense resistor are alternatively measured. These voltage drops may be digitized and used to compute a resistance of the load using, e.g., a digital processor.

Abstract: Techniques for adaptive gain adjustment in a signal processing path to achieve greater dynamic range. In an exemplary embodiment, a digital gain is applied to a digital input signal based on a detected level of the digital input signal. A corresponding analog gain is applied to the output of a digital-to-analog converter for converting the digital input signal to an analog signal, the product of the digital gain and the analog gain being kept constant. In an exemplary embodiment, a zero cross detector is employed to update the digital and analog gains only in the vicinity of zero crossings detected in the signal. In a further exemplary embodiment, a peak detector is employed to instantaneously adjust the digital and analog gains to avoid clipping in the signal path.

Abstract: A switched-capacitor DC blocking amplifier is disclosed. In an embodiment, an integrated circuit is provided that includes an amplifier having an amplifier input and an amplifier output, a capacitor connected to the amplifier input and configured to receive an input signal, and a switched capacitor circuit coupled to provide a resistance between the amplifier input and the amplifier output. In one implementation, the switched capacitor circuit is configured with a feed forward circuit to reduce aliasing. In another implementation, the switched capacitor circuit includes a switched impedance circuit to reduce noise.

Abstract: Techniques for electrostatic discharge (ESD) protection for amplifiers and other circuitry employing charge pumps. In an exemplary embodiment, a Vneg switch coupling a second flying capacitor node to a negative output voltage node is closed in response to an ESD event being detected between a supply voltage node and the negative output voltage node. A ground switch coupling a ground node to the second flying capacitor node is closed in response to an ESD event being detected between the ground node and the negative output voltage node. The Vneg switch is further closed in response to the ESD event being detected between the ground node and the negative output voltage node. Further techniques are disclosed for providing on-chip snapback clamps at the output of a power amplifier coupled to the charge pump to protect against ESD events as defined by the standard IEC 61000-4-2.

Abstract: Techniques for utilizing a plurality of switches to reduce crosstalk in a headset jack for accommodating both European and North American type headset plugs. In an aspect, a six-switch solution is provided to selectively couple first and second terminals of the jack to a ground and a microphone terminal, and further to selectively couple a ground sensing input to the first or second terminal of the jack. The ground sensing input is provided to left and right audio channel amplifiers for driving the corresponding left and right terminals of the headset, to provide a common-mode reference level to the left and right audio channel amplifiers. In another aspect, at least four physical pins are provided to couple the switches to the ground and microphone terminals of the jack, and the connections between the ground sensing inputs and the jack may be provided adjacent to the jack for better isolation.

Abstract: Techniques for designing a transconductor configurable to have a low transconductance. In one aspect, a voltage to current conversion module is coupled to a 1:N current replication module. The voltage to current conversion module may be implemented as an operational amplifier configured with negative feedback to generate a current through a transistor, wherein such current is proportional to the difference between an input voltage and a common-mode reference. The 1:N current replication module is configured to mirror the generated current in another transistor, to a predetermined ratio, such that the output current is also proportional to the difference between the input voltage and the common-mode reference. In exemplary embodiments, the output stage driving the output current may be configured to operate as a Class A, Class B, or Class AB type amplifier.

Abstract: A digital offset is combined with an audio signal in the digital domain to cancel an output offset caused by one or more analog components processing the same audio signal. In this manner, the offset at the output of the audio signal path (e.g., at a power amplifier output) is reduced or eliminated. Consequently, audible artifacts, such as click-and-pop artifacts, can be reduced or eliminated. In audio devices operating in ground-referenced capless mode, power consumption is reduced because of reduced or eliminated direct current (DC) leakage current through speakers or headsets of such audio devices. In some circumstances, the digital offset in the digital domain may be applied at substantially all times of operation of the audio signal path.

Abstract: A switched-capacitor DC blocking amplifier is disclosed. In an embodiment, an integrated circuit is provided that includes an amplifier having an amplifier input and an amplifier output, a capacitor connected to the amplifier input and configured to receive an input signal, and a switched capacitor circuit coupled to provide a resistance between the amplifier input and the amplifier output. In one implementation, the switched capacitor circuit is configured with a feed forward circuit to reduce aliasing. In another implementation, the switched capacitor circuit includes a switched impedance circuit to reduce noise.

Abstract: Techniques for reducing surge current in charge pumps. In an exemplary embodiment, one or more switches coupling a terminal of a flying capacitor to a voltage supply are configured to have variable on-resistance. When the charge pump is configured to switch a gain mode from a lower gain to a higher gain, the one or more variable resistance switches are configured to have a decreasing resistance profile over time. In this manner, surge current drawn from the voltage supply at the outset of the gain switch may be limited, while the on-resistance during steady-state charging and discharging may be kept low. Similar techniques are provided to decrease the surge current from a bypass switch coupling the supply voltage to a positive output voltage of the charge pump.