Abstract: Techniques for providing execution verification at an integrated circuit device are described. The integrated circuit device may include a processor core configured to execute instructions. The integrated circuit device may also include a trace block configured to extract an execution trace from the processor core, the execution trace indicating the instructions that have been executed by the processor core. The integrated circuit device may further include a verification core configured to receive the execution trace from the trace block, extract an address from a control transfer instruction in the execution trace, perform one or more checks on the address, and generate an alarm signal based on the one or more checks.

Abstract: Techniques for providing remote attestation at an integrated circuit device are described. The integrated circuit device may include a memory. The integrated circuit device may also include a write bitmap comprising a bitmap that tracks the write addresses of detected memory write operations to the memory. The integrated circuit device may further include a security subsystem configured to send one or more address ranges of interest to the write bitmap and obtain a bitmap status from the write bitmap indicating that a write address within the one or more address ranges of interest was detected.

Abstract: Methods, systems, and apparatus, including a managed device comprising memory storage, one or more control registers, and circuitry to perform operations of receiving, from a control system, one or more posted write operations directed to the one or more control registers; based on the one or more posted write operations, storing in the one or more control registers, data specifying at least a system address of a memory of the control system, where the system address corresponds to a starting address of a predetermined section of the memory; and transferring managed device data from the memory storage to the predetermined section of the memory of the control system by issuing, to the control system and based on the system address of the memory, one or more posted write operations to write the managed device data to the predetermined section of the memory.

Abstract: Approaches, techniques, and mechanisms are disclosed for maintaining efficient representations of prefix tables for utilization during the operation of a network device. In an embodiment, the performance of a network device is greatly enhanced using a working representation of a prefix table that includes a prefix index and a plurality of associated prefix arrays. In an embodiment, this working representation is bifurcated across a higher-performing memory for the prefix index and a lower-performing memory for the prefix arrays. In an embodiment, management of this working representation is greatly simplified using a sharded prefix tree that is divided into subtrees based on constraints of the memory in which this working representation is stored. In yet another embodiment, a sharded prefix tree may itself be utilized to more efficiently find a longest prefix match for an input key.