Patents by Inventor Gustavo J. Mehas

Gustavo J. Mehas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7256623
    Abstract: A frequency programmable feed forward oscillator and triangular wave generator is disclosed having a first input for receiving an input voltage and a second input for receiving an input current. Circuitry within the device responsive to the input voltage scales the amplitude of a triangle wave form according to the provided input voltage and provides the scaled output voltage at a first output. In conjunction, the circuitry also generates a scaled PWM frequency responsive to the provided input current and provides this at a second output.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: August 14, 2007
    Assignee: Intersil Americas Inc.
    Inventors: Brandon D. Day, James W. Leith, Gustavo J. Mehas
  • Patent number: 7227731
    Abstract: Apparatus for providing over-current protection in a power converter device includes a first circuit for providing high-side sinking over-current protection for the power converter device responsive to a phase signal and a high-side over-current signal of the power converter device. A second circuit provides low-side sinking over-current protection for the power converter device responsive to the phase signal and the low-side over-current signal of the power converter device. Finally, a third circuit provides low-side sourcing over-current protection responsive to the phase signal, the low-side over-current protection signal and a power ground signal of the power converter device.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: June 5, 2007
    Assignee: Intersil Americas Inc.
    Inventors: James W. Leith, Gustavo J. Mehas, Brandon D. Day
  • Patent number: 7088600
    Abstract: An apparatus for reducing surge currents during startup of a voltage regulator is disclosed that includes circuitry for maintaining a voltage at an FB pin of the voltage regulator substantially equivalent to an output voltage of the voltage regulator.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: August 8, 2006
    Assignee: Intersil Americas, Inc.
    Inventors: Gustavo J. Mehas, James W. Leith, Brandon D. Day
  • Patent number: 7038514
    Abstract: A startup circuit for a power converter including an amplifier circuit, a comparator, and startup logic. The power converter includes an error amplifier that compares an output sense signal with a startup reference signal and that provides a compensation signal. The amplifier circuit charges the startup reference signal to a predetermined reference level based on a second reference signal in response to a start signal. The comparator determines when the compensation signal reaches a predetermined ramp level and asserts a startup complete signal indicative thereof. The startup logic provides the start signal and provides an output enable signal in response to the startup complete signal. The output enable signal enables output switching to initiate normal regulation operation of the output voltage. In one embodiment, the predetermined ramp level is approximately the center voltage of a sawtooth regulation waveform used for PWM modulation.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: May 2, 2006
    Assignee: Intersil Americas Inc.
    Inventors: James W. Leith, Gustavo J. Mehas
  • Patent number: 7034586
    Abstract: A method of starting a DC—DC converter into a precharged output voltage including generating a reference voltage having a linear relationship with the output voltage such that the reference voltage ranges between a minimum and maximum voltage level of a PWM triangular waveform as the output voltage ranges between zero and an input voltage level, and enabling output switching of the DC—DC converter when the reference voltage is approximately equal to a compensation signal generated by an error amplifier comparing the reference voltage with a feedback signal representative of the output voltage. Generating a reference voltage may include applying a first current based on the input voltage through two resistors to develop the minimum and maximum voltage levels, applying the first current in one direction through a third resistor, and applying a second current based on the output voltage through the third resistor in the opposite direction.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: April 25, 2006
    Assignee: Intersil Americas Inc.
    Inventors: Gustavo J. Mehas, James W. Leith, Brandon D. Day
  • Patent number: 6975163
    Abstract: An IC including a margining control amplifier circuit, first and second offset pins, a margining control pin, select logic, and a mirror amplifier circuit. The margining control amplifier circuit drives current at an output to control voltage at an input based on a reference voltage. The first and second offset pins are provided to couple an external margining voltage divider. The margining control pin has at least two states including an up state and a down state. The select logic selectively switches the output of the margining control amplifier circuit between the first and second offset pins and selectively switches the input of the margining control amplifier circuit between the second and first offset pins based on a state of the margining control pin. The mirror amplifier circuit mirrors voltage across the first and second offset pins across a first margining resistor.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: December 13, 2005
    Assignee: Intersil Americas, Inc.
    Inventors: Gustavo J. Mehas, James W. Leith, Brandon D. Day