Patents by Inventor Gweltaz Gaudin

Gweltaz Gaudin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8999090
    Abstract: The invention relates to a method for bonding two substrates, in particular, two semiconductor substrates that, in order to be able to improve the reliability of the process, provides the step of providing a gaseous flow over the bonding surfaces of the substrates. The gaseous flow is preferably a laminar flow that is essentially parallel to the bonding surfaces of the substrates, and has a temperature in a range of from room temperature up to 100° C.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: April 7, 2015
    Assignee: SOITEC
    Inventors: Gweltaz Gaudin, Fabrice Lallement, Cyrille Colnat, Pascale Giard
  • Publication number: 20140327113
    Abstract: The invention relates to a process for assembling a first element that includes at least one first wafer, substrate or at least one chip, and a second element of at least one second wafer or substrate, involving the formation of a surface layer, known as a bonding layer, on each substrate, at least one of the bonding layers being formed at a temperature less than or equal to 300° C.; conducting a first annealing, known as degassing annealing, of the bonding layers, before assembly, at least partly at a temperature at least equal to the subsequent bonding interface strengthening temperature but below 450° C.; forming an assembling of the substrates by bringing into contact the exposed surfaces of the bonding layers, and conducting an annealing of the assembled structure at a bonding interface strengthening temperature below 450° C.
    Type: Application
    Filed: July 17, 2014
    Publication date: November 6, 2014
    Inventor: Gweltaz Gaudin
  • Publication number: 20140225182
    Abstract: A substrate comprises a base wafer, an insulating layer over the base wafer, and a top semiconductor layer over the insulating layer on a side thereof opposite the base wafer. The insulating layer comprises a charge-confining layer confined on one or both sides with diffusion barrier layers, wherein the charge-confining layer has a density of charges in absolute value higher than 1010 charges/cm2. Alternatively, the insulating layer comprises charge-trapping islands embedded therein, wherein the charge-trapping islands have a total density of charges in absolute value higher than 1010 charges/cm2.
    Type: Application
    Filed: April 15, 2014
    Publication date: August 14, 2014
    Applicant: Soitec
    Inventors: Mohamad A. Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure
  • Patent number: 8790992
    Abstract: The invention relates to a process for assembling a first element that includes at least one first wafer, substrate or at least one chip, and a second element of at least one second wafer or substrate, involving the formation of a surface layer, known as the bonding layer, on each substrate, at least one of these bonding layers being formed at a temperature less than or equal to 300° C.; conducting a first annealing, known as degassing annealing, of the bonding layers, before assembly, at least partly at a temperature at least equal to the subsequent bonding interface strengthening temperature but below 450° C.; forming an assembling of the substrates by bringing into contact the exposed surfaces of the bonding layers, and conducting an annealing of the assembled structure at a bonding interface strengthening temperature below 450° C.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: July 29, 2014
    Assignee: Soitec
    Inventor: Gweltaz Gaudin
  • Patent number: 8735946
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: May 27, 2014
    Assignee: Soitec
    Inventors: Mohamad A Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure
  • Publication number: 20140015023
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Application
    Filed: September 16, 2013
    Publication date: January 16, 2014
    Applicant: Soitec
    Inventors: Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure, Mohamad A. Shaheen
  • Patent number: 8603896
    Abstract: A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: December 10, 2013
    Assignee: Soitec
    Inventors: Gweltaz Gaudin, Carlos Mazure
  • Patent number: 8575002
    Abstract: A method for the direct bonding of a first wafer having an intrinsic curvature before bonding to a second wafer having an intrinsic curvature before bonding, at least one of the two wafers including at least one series of microcomponents. The method includes bringing the two wafers into contact with each other so as to initiate the propagation of a bonding wave therebetween while imposing a predefined bonding curvature in the form of a paraboloid of revolution on one of the two wafers depending at least upon the intrinsic curvature before bonding of the wafer that includes the microcomponents, with the other wafer being free to conform to the predefined bonding curvature.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: November 5, 2013
    Assignee: Soitec
    Inventors: Marcel Broekaart, Gweltaz Gaudin, Arnaud Castex
  • Patent number: 8535996
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: September 17, 2013
    Assignee: SOITEC
    Inventors: Mohamad Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karin Landry, Carlos Mazure
  • Patent number: 8475612
    Abstract: A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: July 2, 2013
    Assignee: Soitec
    Inventor: Gweltaz Gaudin
  • Publication number: 20130029474
    Abstract: A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 31, 2013
    Applicant: SOITEC
    Inventors: Gweltaz Gaudin, Carlos Mazure
  • Patent number: 8202785
    Abstract: A method of bonding a first substrate to a second substrate by molecular bonding by forming an insulating layer on the bonding face of the first substrate, chemical-mechanical polishing of the insulating layer, activating a bonding surface of the second substrate by plasma treatment, etching an exposed surface of the insulating layer, and bonding together the two substrates together by molecular bonding wherein the etching is conducted after the chemical-mechanical polishing and before the bonding.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: June 19, 2012
    Assignee: Soitec
    Inventors: Arnaud Castex, Gweltaz Gaudin, Marcel Broekaart
  • Publication number: 20120077329
    Abstract: A method for the direct bonding of a first wafer having an intrinsic curvature before bonding to a second wafer having an intrinsic curvature before bonding, at least one of the two wafers comprising at least one series of microcomponents. The method includes of bringing the two wafers into contact with each other so as to initiate the propagation of a bonding wave therebetween while imposing a predefined bonding curvature in the form of a paraboloid of revolution on one of the two wafers depending at least upon the intrinsic curvature before bonding of the wafer that includes the microcomponents, with the other wafer being free to conform to the predefined bonding curvature.
    Type: Application
    Filed: July 28, 2011
    Publication date: March 29, 2012
    Inventors: Marcel Broekaart, Gweltaz Gaudin, Arnaud Castex
  • Publication number: 20120015497
    Abstract: A method of fabricating a heterostructure comprising at least a first substrate (120) made of sapphire and a second substrate (110) made of a material having a coefficient of thermal expansion that is different from that of the first substrate. The method includes a step (S6) of molecular bonding the second substrate (110) on the first substrate (120) made of sapphire. The method also includes, prior to bonding the two substrates together, a step (S1) of stoving the first substrate (120) at a temperature that lies in the range 100° C. to 500° C.
    Type: Application
    Filed: November 16, 2009
    Publication date: January 19, 2012
    Inventors: Gweltaz Gaudin, Mark Kennard, Matteo Piccin, Ionut Radu, Alexandre Vaufredaz
  • Publication number: 20120006463
    Abstract: A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment.
    Type: Application
    Filed: October 4, 2010
    Publication date: January 12, 2012
    Inventor: Gweltaz Gaudin
  • Publication number: 20110195560
    Abstract: The invention provides a method of producing a heterostructure of the silicon-on-sapphire type, comprising bonding an SOI substrate onto a sapphire substrate and thinning the SOI substrate, thinning being carried out by grinding followed by etching of the SOI substrate. In accordance with the method, grinding is carried out using a wheel with a grinding surface that comprises abrasive particles having a mean dimension of more than 6.7 ?m; further, after grinding and before etching, the method comprises a step of post-grinding annealing of the heterostructure carried out at a temperature in the range of 150° C. to 170° C.
    Type: Application
    Filed: November 19, 2009
    Publication date: August 11, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Gweltaz Gaudin, Alexandre Vaufredaz, Fleur Guittard
  • Publication number: 20110189834
    Abstract: A method of bonding a first substrate to a second substrate by molecular bonding by forming an insulating layer on the bonding face of the first substrate, chemical-mechanical polishing of the insulating layer, activating a bonding surface of the second substrate by plasma treatment, etching an exposed surface of the insulating layer, and bonding together the two substrates together by molecular bonding wherein the etching is conducted after the chemical-mechanical polishing and before the bonding.
    Type: Application
    Filed: October 27, 2009
    Publication date: August 4, 2011
    Applicant: S.O.I. Tec Silicon on Insulator Technologies Parc Technologique dws Fontaines
    Inventors: Arnaud Castex, Gweltaz Gaudin, Marcel Broekaart
  • Publication number: 20110012200
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Application
    Filed: March 13, 2008
    Publication date: January 20, 2011
    Applicant: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Mohamad Shaheen, Carlos Mazure
  • Publication number: 20110000612
    Abstract: The invention relates to a method for bonding two substrates, in particular two semiconductor substrates which, in order to be able to improve the reliability of the process, provides the step of providing a gaseous flow over the bonding surfaces of the substrates The invention also relates to a corresponding bonding equipment
    Type: Application
    Filed: January 23, 2009
    Publication date: January 6, 2011
    Inventors: Gweltaz Gaudin, Fabrice Lallement, Cyrille Colnat, Pascale Giard