Abstract: A technique is provided for increasing the pixel pitch without increasing the interconnect density of a digital detector. Generally, a digital detector has an array of rows and columns of pixels, read out electronics and scan electronics, that are configured to generate and transmit signals based upon radiation impacting the detector. The detector also having a plurality of scan lines, which are coupled to the plurality of rows of pixels. The present technique also provides a multiplexing circuit for selectively coupling the rows of pixels to the respective scan lines for read out of the signals.

Abstract: An x-ray system (10) include a digital detector (400) that defines two regions: a first region (404) suitable for generating data useful for creating a patient x-ray image and a second region (406) less suitable for generating such data than the first region. A source (20) transmits x-rays through a phantom (420) located between the source and the second region (406) so that the detector (400) generates test data in the second region. A processor (302) measures at least one parameter in response to the test data and stores a value of the parameter at one point of time. The processor compares the first value with a second value of the one parameter generated at a later second point in time. The processor also generates a result signal representing the results of the comparison.

Abstract: An x-ray system (10) include a digital detector (400) that defines two regions: a first region (404) suitable for generating data useful for creating a patient x-ray image and a second region (406) less suitable for generating such data than the first region. A source (20) transmits x-rays through a phantom (420) located between the source and the second region (406) so that the detector (400) generates test data in the second region. A processor (302) measures at least one parameter in response to the test data and stores a value of the parameter at one point of time. The processor compares the first value with a second value of the one parameter generated at a later second point in time. The processor also generates a result signal representing the results of the comparison.

Abstract: A method and apparatus for correcting electronic offset and gain variations in solid state x-ray detectors includes dedicating rows at the end of an x-ray detector scan. The dedicated rows may be used to measure the “signal” induced by electronic offset and gain variations in solid state x-ray detectors. The first row may be used to measure the signal induced by electronic offset. The second row may be used to measure to signal induced by gain variations. Measurements of the induced signals taken from the dedicated rows may be used to eliminate structured artifacts from the x-ray image.

Abstract: A technique is provided for increasing the pixel pitch without increasing the interconnect density of a digital detector. Generally, a digital detector has an array of rows and columns of pixels, read out electronics and scan electronics, that are configured to generate and transmit signals based upon radiation impacting the detector. The detector also having a plurality of scan lines, which are coupled to the plurality of rows of pixels. The present technique also provides a multiplexing circuit for selectively coupling the rows of pixels to the respective scan lines for read out of the signals.

Abstract: The present invention, in one form, is a flexible interconnect circuit for altering the resolution of an imaging system. In one embodiment, by combining a plurality of detector array signal lines within the interconnect circuit, the imaging system resolution is altered. Each interconnect circuit includes a plurality of contacts at a first end and a second end and a plurality of conductors extending therebetween electrically connected to at least one contact at each end. By altering the number of contacts which are connected together, the resolution of the imaging system is altered.

Abstract: A method is provided for maximizing substrate usage in the fabrication of flat panel displays or detectors, while also maximizing electrostatic protection for the displays or detectors. Initially, at least two detectors are positioned on the substrate, with each of the detectors having a guard ring of a certain width. At least a section of the guard ring width of one detector is approximately adjacent to a section of the guard ring width of another detector. The approximately adjacent guard ring width sections are then positioned such that a maximum overlap of the adjacent guard ring width sections is achieved, while still providing each display or detector with electrostatic discharge protection. Each of the detectors is separated from the other detectors and the remainder of the substrate by the process of scribing partially through the substrate and breaking at the scribe mark or by sawing.

Abstract: An imager array includes a substrate with a plurality of superimposed layers of electrically conductive and active components. Sets of scan and data lines are electrically insulated from one another and also from a common electrode and active array components by dielectric material. Protection of the active components against static charge potential includes resistive means between the common electrode and a ground ring conductor around the array elements and in particular a thin film transistor circuit with a parallel pair of opposite polarity diode connected field effect transistors to safely drain the static charge during subsequent fabrication, test and standby period of the imager, while remaining in circuit during imager operation.

Abstract: Interconnect carriers for coupling integrated circuit chips to major substrates and methods for making the same are disclosed. The interconnect carrier comprises a relatively thin resilient supporting layer, a plurality of electrically conductive vias formed through the surfaces of the supporting layer, and an outer frame disposed around the periphery of the supporting layer. The supporting layer preferably comprises an electrically insulating material. The flexibility of the supporting layer enables the layer to more readily conform to the warpages of the IC chip and supporting substrate, while the outer frame provides mechanical support and prevents the supporting layer from folding, twisting, and/or stretching. The thickness of the supporting layer may be substantially reduced over that of prior art interposers to enable methods for constructing smaller diameter vias.