Abstract: A system and method for providing memory device readiness to a memory controller is disclosed. One example system includes a channel controller operably connected to a memory controller and a group of flash memory devices. The channel controller may receive, from the memory controller a request for a status of one or more memory devices in the group of flash memory devices. The channel controller may determine the status of the one or more memory devices, the status being determined while the memory controller is permitted to execute one or more other commands related to one or more other memory devices in a different group of memory devices. On determining that the one or more memory devices are in a ready status, the channel controller may provide the ready status to the memory controller.

Abstract: The present disclosure relates to systems and methods for providing high performance Redundant Array of Independent Disks (RAID) in a solid-state device. The present disclosure includes a solid state device. The solid state device can include a buffer having a plurality of bit cells, configured to maintain a plurality of bits of information. The solid state device can also include a memory controller configured to logically partition the plurality of bit cells into a plurality of logical blocks, each configured to maintain a data block. The solid state device can additionally include a RAID engine coupled to the buffer, where the buffer is configured to provide data blocks to the RAID engine, and in response, the RAID engine is configured to compute first parity bits from the data blocks and directly provide the first parity bits to one of a plurality of flash memory devices.

Abstract: A system and method for providing memory device readiness to a memory controller is disclosed. One example system includes a channel controller operably connected to a memory controller and a group of flash memory devices. The channel controller may receive, from the memory controller a request for a status of one or more memory devices in the group of flash memory devices. The channel controller may determine the status of the one or more memory devices, the status being determined while the memory controller is permitted to execute one or more other commands related to one or more other memory devices in a different group of memory devices. On determining that the one or more memory devices are in a ready status, the channel controller may provide the ready status to the memory controller.