Abstract: A semiconductor memory apparatus includes a memory circuit unit, a radio frequency (RF) signal unit which wirelessly transmits and receives signals, and a control circuit unit which accesses the memory circuit unit in response to a signal received through the RF signal unit and provides data of the memory circuit unit to the RF signal unit. At least one of the RF signal unit and the control circuit unit has a one-chip structure with the memory circuit unit.

Abstract: A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.

Abstract: An electronic device includes semiconductor memory, which includes a memory cell block including first and second cell arrays and a column control block. The first cell array includes a word line, a first bit line, and a first variable resistance layer disposed between the word line and the first bit line. The second cell array includes the word line, a second bit line crossing the word line and the first bit line, and a second variable resistance layer disposed between the word line and the second bit line. The first and second variable resistance layers include different materials. The column control block supplies a first write bias for switching a resistance state of the first variable resistance layer to the first bit line and a second write bias for switching a resistance state of the second variable resistance layer to the second bit line.

Abstract: A semiconductor apparatus includes a variable resistor including a variable resistance layer, which is formed to surround on an inner surface of a resistive region, and an insert layer which is formed in the variable resistance layer and has a resistivity being different from that of the variable resistance layer.

Abstract: A method for fabricating a semiconductor apparatus includes forming a diffusion barrier film on a semiconductor substrate, forming a first film on a semiconductor substrate including a common source region, forming a second film on the first film, forming a conductive film on the second film, patterning the conductive film and the second film, to form an active pattern, and patterning the first film and the semiconductor substrate using the active pattern as a mask, to form a pillar; and forming a gate electrode on an outer circumference of the pillar.

Abstract: A high voltage generating circuit for a resistive memory apparatus is provided. The high voltage generating circuit includes a capacitor spaced from a semiconductor substrate and electrically insulated from the semiconductor substrate. A switching device, which is electrically connected to the capacitor, is electrically insulated from the semiconductor substrate.

Abstract: A semiconductor integrated circuit device having a reservoir capacitor and a method of manufacturing the same are provided. A first insulating layer is formed on a semiconductor substrate including a first region and a second region. A first conductive layer is formed on the first insulating layer, and a second insulating layer is formed on the first conductive layer. The second insulating layer is patterned to be left in a portion of the first region. A second conductive layer is formed on the second insulating layer and the first conductive layer. The second conductive layer is etched to expose a partial surface of the first conductive layer in the first region. The second conductive layer and the first conductive layer are etched to form a reservoir capacitor in the first region and form a gate in the second region.

Abstract: An electronic device includes a semiconductor memory circuit. The semiconductor memory circuit includes a plurality of first conductive lines which includes an anti-oxidation layer on both sides of each first conductive line, an inter-layer dielectric layer suitable for gap-filling a space between the first conductive lines, a material layer formed over the first conductive lines and the inter-layer dielectric layer and including oxygen vacancies, and a plurality of second conductive lines formed over the material layer to intersect with the first conductive lines. A first portion of the material layer where the first conductive lines and the second conductive lines overlap each other has a lower oxygen content than a second portion of the material layer where the inter-layer dielectric layer and the second conductive lines overlap each other.

Abstract: An electronic device includes semiconductor memory, which includes a memory cell block including first and second cell arrays and a column control block. The first cell array includes a word line, a first bit line, and a first variable resistance layer disposed between the word line and the first bit line. The second cell array includes the word line, a second bit line crossing the word line and the first bit line, and a second variable resistance layer disposed between the word line and the second bit line. The first and second variable resistance layers include different materials. The column control block supplies a first write bias for switching a resistance state of the first variable resistance layer to the first bit line and a second write bias for switching a resistance state of the second variable resistance layer to the second bit line.

Abstract: A resistive memory apparatus includes a memory unit including a resistive memory cell array, a voltage generation unit suitable for receiving a radio frequency (RF) signal, and converting the RF signal into a direct current (DC) voltage, and a control unit suitable for controlling a refresh operation to be performed on the resistive memory cell array, wherein the boosted DC voltage is used as an operation voltage for the refresh operation.

Abstract: A method for fabricating a semiconductor apparatus includes forming a diffusion barrier film on a semiconductor substrate, forming a semiconductor film on the semiconductor substrate in which the diffusion barrier film is formed, forming a silicide film on the semiconductor film, forming a conductive film on the silicide film, forming an upper portion of a pillar structure in a first region of the semiconductor substrate by patterning the conductive film, the silicide film, and the semiconductor film, forming a lower portion of the pillar structure by patterning the diffusion barrier film and the semiconductor substrate in the first region, and forming a gate electrode on an outer side of a patterned semiconductor substrate.

Abstract: A high voltage generating circuit for a resistive memory apparatus is provided. The high voltage generating circuit includes a capacitor spaced from a semiconductor substrate and electrically insulated from the semiconductor substrate. A switching device, which is electrically connected to the capacitor, is electrically insulated from the semiconductor substrate.

Abstract: A resistive memory apparatus includes a memory region including a plurality of resistive memory cells, and a controller suitable for storing a threshold number of write operations according to a data storage material of the resistive memory cells, counting numbers of write operations for the respective resistive memory cells as a write operation is performed for the memory region, and performing interrupt control when a memory cell that reaches the threshold number of write operations is detected.

Abstract: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.

Abstract: A resistive memory device capable of preventing disturbance is provided. The resistive memory device includes a lower electrode formed on a semiconductor substrate, a variable resistor disposed on the lower electrode, an upper electrode disposed on the variable resistor, and an interlayer insulating layer configured to insulate the variable resistor. The interlayer insulating layer may include an air-gap area in at least a portion thereof.

Abstract: An electronic device includes a semiconductor memory circuit. The semiconductor memory circuit includes a plurality of first conductive lines which includes an anti-oxidation layer on both sides of each first conductive line, an inter-layer dielectric layer suitable for gap-filling a space between the first conductive lines, a material layer formed over the first conductive lines and the inter-layer dielectric layer and including oxygen vacancies, and a plurality of second conductive lines formed over the material layer to intersect with the first conductive lines. A first portion of the material layer where the first conductive lines and the second conductive lines overlap each other has a lower oxygen content than a second portion of the material layer where the inter-layer dielectric layer and the second conductive lines overlap each other.

Abstract: A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.

Abstract: A resistive memory apparatus includes a memory unit including a resistive memory cell array, a voltage generation unit suitable for receiving a radio frequency (RF) signal, and converting the RF signal into a direct current (DC) voltage, and a control unit suitable for controlling a refresh operation to be performed on the resistive memory cell array, wherein the boosted DC voltage is used as an operation voltage for the refresh operation.

Abstract: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.

Abstract: A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level.