Abstract: There is provided a VIL system-based autonomous driving function verification method. According to embodiments of the disclosure, a VIL system enables an autonomous vehicle to verify an autonomous driving function by interlocking with a virtual road environment in any other place, without having to go to a real test road corresponding to a simulated virtual road environment. Accordingly, an autonomous driving function can be rapidly verified based on a VIL system with respect to various virtual road environments without changing a driving place, so that speed and convenience in development of autonomous driving technology can be enhanced.

Abstract: Provided is a tiled display device including a plurality of display devices each having a display panel including a plurality of pixels and a support plate disposed under the display panel, a lower cover including an alignment hole and coupled to a lower portion of the support plate of each of the plurality of display devices, and a first coupling member including a base portion fixed to the support plate and a first coupling portion protruding from the base portion and passing through the alignment hole. A diameter of the first coupling portion is smaller than a diameter of the alignment hole.

Abstract: A display device includes a first heat dissipation member disposed on a display panel, and an air generator disposed on the first heat dissipation member, wherein the air generator includes an air blower, and an air flow path disposed at a side of the air blower and extending in a first direction. The air blower includes a body defining an inner space of the air blower, a first diaphragm and a second diaphragm disposed in the inner space of the body and facing each other, a first magnet disposed on a surface of the first diaphragm, and a second magnet disposed on a surface of the second diaphragm, and an air discharge hole of the body disposed between the first diaphragm and the second diaphragm, the air discharge hole opened toward the air path, and at least one of the first magnet and the second magnet is an electromagnet.

Abstract: A pixel includes a first electrode and a second electrode spaced from each other in a first direction on a substrate; a plurality of light emitting elements between the first electrode and the second electrode; an intermediate pattern located between the first electrode and the second electrode in the first direction and located between the substrate and the plurality of light emitting elements in a thickness direction of the substrate; a first contact electrode electrically connecting one end portion of each of the light emitting elements and the first electrode; and a second contact electrode electrically connecting an other end portion of each of the light emitting elements and the second electrode.

Abstract: The present invention relates to a display device. Specifically, a display device according to an embodiment of the present invention includes pixels and a data driver, wherein each of the pixels includes a first light-emitting diode aligned in a first direction; a first pixel circuit for driving the first light-emitting diode; a second light-emitting diode aligned in a second direction; and a second pixel circuit for driving the second light-emitting diode, and wherein the data driver supplies a first data signal to the first pixel circuit, and supplies a second data signal to the second pixel circuit during one frame period.

Abstract: A display device includes a first heat dissipation member disposed on a display panel, and an air generator disposed on the first heat dissipation member, wherein the air generator includes an air blower, and an air flow path disposed at a side of the air blower and extending in a first direction. The air blower includes a body defining an inner space of the air blower, a first diaphragm and a second diaphragm disposed in the inner space of the body and facing each other, a first magnet disposed on a surface of the first diaphragm, and a second magnet disposed on a surface of the second diaphragm, and an air discharge hole of the body disposed between the first diaphragm and the second diaphragm, the air discharge hole opened toward the air path, and at least one of the first magnet and the second magnet is an electromagnet.

Abstract: A pixel includes a first electrode and a second electrode spaced from each other in a first direction on a substrate; a plurality of light emitting elements between the first electrode and the second electrode; an intermediate pattern located between the first electrode and the second electrode in the first direction and located between the substrate and the plurality of light emitting elements in a thickness direction of the substrate; a first contact electrode electrically connecting one end portion of each of the light emitting elements and the first electrode; and a second contact electrode electrically connecting an other end portion of each of the light emitting elements and the second electrode.

Abstract: Provided is a tiled display device including a plurality of display devices each having a display panel including a plurality of pixels and a support plate disposed under the display panel, a lower cover including an alignment hole and coupled to a lower portion of the support plate of each of the plurality of display devices, and a first coupling member including a base portion fixed to the support plate and a first coupling portion protruding from the base portion and passing through the alignment hole. A diameter of the first coupling portion is smaller than a diameter of the alignment hole.

Abstract: The present invention relates to a display device. Specifically, a display device according to an embodiment of the present invention includes pixels and a data driver, wherein each of the pixels includes a first light-emitting diode aligned in a first direction; a first pixel circuit for driving the first light-emitting diode; a second light-emitting diode aligned in a second direction; and a second pixel circuit for driving the second light-emitting diode, and wherein the data driver supplies a first data signal to the first pixel circuit, and supplies a second data signal to the second pixel circuit during one frame period.

Abstract: A display device a includes: a display portion including pixels arranged in a matrix form; gate lines extending in a row direction for each pixel row and connected to the pixels; and a gate driver which applies a gate signal of a gate-on voltage to the plurality of gate lines. The gate driver applies the gate signal in the order of a k-th gate line, a (k+3)-th gate line, a (k+1)-th gate line, a (k+4)-th gate line, a (k+2)-th gate line, and a (k+5)-th gate line, where k is an integer greater than 1, and pixels connected to the k-th gate line and the (k+3)-th gate line display a first color, pixels connected to the (k+1)-th gate line and the (k+4)-th gate line display a second color, and pixels connected to the (k+2)-th gate line and the (k+5)-th gate line display a third color.

Abstract: A display includes: pixels arranged in a display area (DA) in a first direction (FD) and a second direction (SD), each pixel to display one of first to third colors; gate lines (GLs) extending in the FD in the DA, arranged in the SD, and connected to the pixels; a stage unit (SU) in a non-DA, the SU including stages and being connected to the GLs; clock lines (CLs) to receive signals to control the SU, the CLs extending in the SD in the non-DA and being arranged in the FD; and bridge lines connecting the CLs with the SU. First and second CLs are connected to stages connected to pixels to display the first color. Third and fourth CLs are connected to stages connected to pixels to display the second color. Fifth and sixth CLs are connected to stages connected to pixels to display the third color.

Abstract: A display includes: pixels arranged in a display area (DA) in a first direction (FD) and a second direction (SD), each pixel to display one of first to third colors; gate lines (GLs) extending in the FD in the DA, arranged in the SD, and connected to the pixels; a stage unit (SU) in a non-DA, the SU including stages and being connected to the GLs; clock lines (CLs) to receive signals to control the SU, the CLs extending in the SD in the non-DA and being arranged in the FD; and bridge lines connecting the CLs with the SU. First and second CLs are connected to stages connected to pixels to display the first color. Third and fourth CLs are connected to stages connected to pixels to display the second color. Fifth and sixth CLs are connected to stages connected to pixels to display the third color.

Abstract: A gate driver includes multiple stages. Each stage has a circuit portion and a wiring portion. The wiring portion delivers first and second clock signals to the circuit portion. Further, the wiring portion includes first and second clock wirings receiving the first and second clock signal, respectively, first connecting wirings electrically connecting the first clock wiring with a first every other stage, and second connecting wirings electrically connecting the second clock wiring with the odd-numbered stages. Further, the wiring portion includes third connecting wirings electrically connecting the first connecting wiring with a second every other stage and fourth connecting wirings electrically connecting the second connecting wiring with the even-numbered stages. This configuration may prevent the gate driver from operating erroneously and reduce power consumed by the gate driver.

Abstract: A display device a includes: a display portion including pixels arranged in a matrix form; gate lines extending in a row direction for each pixel row and connected to the pixels; and a gate driver which applies a gate signal of a gate-on voltage to the plurality of gate lines. The gate driver applies the gate signal in the order of a k-th gate line, a (k+3)-th gate line, a (k+1)-th gate line, a (k+4)-th gate line, a (k+2)-th gate line, and a (k+5)-th gate line, where k is an integer greater than 1, and pixels connected to the k-th gate line and the (k+3)-th gate line display a first color, pixels connected to the (k+1)-th gate line and the (k+4)-th gate line display a second color, and pixels connected to the (k+2)-th gate line and the (k+5)-th gate line display a third color.

Abstract: Gate-driving circuitry of a thin film transistor array panel is formed on the same plane as a display area of the transistor array panel. The gate-driving circuitry includes driving circuitry and signal lines having apertures. Thus, a sufficient amount of light, even though illuminated from the thin film transistor array panel side, can reach a photosetting sealant overlapping at least in part the gate-driving circuitry. The thin film transistor array panel and the counter panel are put together air-tight and moisture-tight. Consequently, the gate-driving circuitry can avoid corrosion by moisture introduced from outside. Gate-driving circuitry malfunctions can also be reduced.

Abstract: A liquid crystal display includes a plurality of pixels disposed in a matrix shape. Each pixel includes a first subpixel electrode and a second subpixel electrode. Two data lines are positioned between two adjacent pixel columns of the plurality of pixels. First subpixel electrodes in a first pixel row and a second pixel row are connected to a first gate line. Second subpixel electrodes in the second pixel row and a third pixel row are connected to a second gate line. A first data voltage applied to the first subpixel electrodes is higher than a second data voltage applied to the second subpixel electrodes. First duration of a first gate signal applied to the first gate line is shorter than second duration of a second gate signal applied to the second gate line.

Abstract: Gate-driving circuitry of a thin film transistor array panel is formed on the same plane as a display area of the transistor array panel. The gate-driving circuitry includes driving circuitry and signal lines having apertures. Thus, a sufficient amount of light, even though illuminated from the thin film transistor array panel side, can reach a photosetting sealant overlapping at least in part the gate-driving circuitry. The thin film transistor array panel and the counter panel are put together air-tight and moisture-tight. Consequently, the gate-driving circuitry can avoid corrosion by moisture introduced from outside. Gate-driving circuitry malfunctions can also be reduced.

Abstract: Gate-driving circuitry of a thin film transistor array panel is formed on the same plane as a display area of the transistor array panel. The gate-driving circuitry includes driving circuitry and signal lines having apertures. Thus, a sufficient amount of light, even though illuminated from the thin film transistor array panel side, can reach a photosetting sealant overlapping at least in part the gate-driving circuitry. The thin film transistor array panel and the counter panel are put together air-tight and moisture-tight. Consequently, the gate-driving circuitry can avoid corrosion by moisture introduced from outside. Gate-driving circuitry malfunctions can also be reduced.

Abstract: A method of driving a display panel includes generating a reference gate signal delayed by a predetermined period from a gate signal applied to a gate line disposed in a first end area of the display panel, the first end area being an area in which a RC delay of a data line is the smallest, receiving an input gate signal applied to a gate line disposed in a second area of the display panel, the second area being an area in which the RC delay of the data line is the largest; and selectively controlling a delay time of each of the plurality of gate signals applied to each of the plurality of gate lines according to a result of comparison between the reference gate signal and the input gate signal.

Abstract: A gate driver includes multiple stages. Each stage has a circuit portion and a wiring portion. The wiring portion delivers first and second clock signals to the circuit portion. Further, the wiring portion includes first and second clock wirings receiving the first and second clock signal, respectively, first connecting wirings electrically connecting the first clock wiring with a first every other stage, and second connecting wirings electrically connecting the second clock wiring with the odd-numbered stages. Further, the wiring portion includes third connecting wirings electrically connecting the first connecting wiring with a second every other stage and fourth connecting wirings electrically connecting the second connecting wiring with the even-numbered stages. This configuration may prevent the gate driver from operating erroneously and reduce power consumed by the gate driver.