Patents by Inventor Hai-Ching Chen

Hai-Ching Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180211911
    Abstract: A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.
    Type: Application
    Filed: March 19, 2018
    Publication date: July 26, 2018
    Inventors: Yung-Hsu Wu, Hai-Ching Chen, Jung-Hsun Tsai, Shau-Lin Shue, Tien-I Bao
  • Publication number: 20180188451
    Abstract: A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 5, 2018
    Inventors: Chun-Hao Tseng, Wan-Yu Lee, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10014175
    Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: July 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee, Ming-Feng Shieh, Ru-Gun Liu, Shau-Lin Shue, Tien-I Bao, Tsai-Sheng Gau, Yung-Hsu Wu
  • Patent number: 10008382
    Abstract: The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: June 26, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Jiun Lin, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20180158725
    Abstract: A method for fabrication a semiconductor device and a system utilizing the same are provided. In the method for fabrication the semiconductor device, at first, a semiconductor structure having a metal conducting structure is provided. Next, a dielectric layer is deposited over the metal conducting structure. Then, an etching process is performed on the dielectric layer by using a fluorine-containing gas so as to form an opening, in which fluorine-containing compounds are formed on a surface of the opening during the etching process. And then, a pre-cleaning process is performed by using UV radiation so as to remove the fluorine-containing compounds. After the pre-cleaning process is performed, a cleaning process is performed to clean the surface of the opening.
    Type: Application
    Filed: February 7, 2017
    Publication date: June 7, 2018
    Inventors: Shao-Kuan Lee, Hsin-Yen Huang, Hai-Ching Chen
  • Publication number: 20180130752
    Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.
    Type: Application
    Filed: January 2, 2018
    Publication date: May 10, 2018
    Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
  • Patent number: 9941157
    Abstract: A method for semiconductor manufacturing includes receiving a device that includes a substrate and a first layer disposed over the substrate, wherein the first layer includes a trench. The method further includes applying a first material over the first layer and filling in the trench, wherein the first material contains a matrix and a porogen that is chemically bonded with the matrix. The method further includes curing the first material to form a porous material layer. The porous material layer has a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed over the first layer. The first and second portions contain substantially the same percentage of each of Si, O, and C. The first and second portions contain substantially the same level of porosity.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Jiun Lin, Ching-Yu Chang, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20180096850
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Application
    Filed: November 22, 2017
    Publication date: April 5, 2018
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • Patent number: 9922927
    Abstract: A first conductive element is disposed in a first dielectric layer. An etching stop layer is disposed on the first dielectric layer but not on the first conductive element. A first metal capping layer segment is disposed on the first conductive element but not on the first dielectric layer. The etching stop layer has a greater thickness than the first metal capping layer segment. A first segment of a second conductive element is disposed on the first metal capping layer segment. A second segment of the second conductive element is disposed over the first segment of the second conductive element and partially over the etching stop layer. A third conductive element is disposed over the second conductive element.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: March 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Hsu Wu, Hai-Ching Chen, Jung-Hsun Tsai, Shau-Lin Shue, Tien-I Bao
  • Publication number: 20180076132
    Abstract: The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer.
    Type: Application
    Filed: November 13, 2017
    Publication date: March 15, 2018
    Inventors: Jung-Hsun Tsai, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao, Chien-Hua Huang
  • Patent number: 9910217
    Abstract: A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: March 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hao Tseng, Wan-Yu Lee, Hai-Ching Chen, Tien-I Bao
  • Patent number: 9905457
    Abstract: A method for forming an interconnect structure includes forming a patterned layer over a substrate, the patterned layer having an opening therein. A dielectric material is filled in the opening. The dielectric material has a precursor and a solvent, the solvent having a boiling point temperature greater than a precursor cross-linking temperature. A thermal treatment is performed on the dielectric material to form a dielectric layer.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: February 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jiun Lin, Ching-Yu Chang, Hai-Ching Chen, Tien-I Bao
  • Patent number: 9892946
    Abstract: A processing apparatus includes a spin coating chamber, an ultraviolet curing chamber, a transfer module and an enclosure. The transfer module is assigned with a plurality transfer destinations, in which two of the transfer destinations are respectively located within the spin coating chamber and the ultraviolet curing chamber. The transfer module, the spin coating chamber and the ultraviolet curing chamber are enclosed by the enclosure.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Fang Cheng, Shao-Kuan Lee, Hai-Ching Chen
  • Publication number: 20180033730
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate and the first conductive structure. The semiconductor device structure includes a second conductive structure over the first conductive structure and extending into the first dielectric layer. The second conductive structure is electrically connected to the first conductive structure. The semiconductor device structure includes a cover layer between the second conductive structure and the first dielectric layer. The cover layer surrounds the second conductive structure, the second conductive structure passes through the cover layer and is partially between the cover layer and the first conductive structure, and the cover layer includes a metal oxide.
    Type: Application
    Filed: October 10, 2017
    Publication date: February 1, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Fang CHENG, Chi-Lin TENG, Hai-Ching CHEN, Hsin-Yen HUANG, Tien-I BAO, Jung-Hsun TSAI
  • Publication number: 20180033653
    Abstract: A processing apparatus includes a spin coating chamber, an ultraviolet curing chamber, a transfer module and an enclosure. The transfer module is assigned with a plurality transfer destinations, in which two of the transfer destinations are respectively located within the spin coating chamber and the ultraviolet curing chamber. The transfer module, the spin coating chamber and the ultraviolet curing chamber are enclosed by the enclosure.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 1, 2018
    Inventors: Kai-Fang Cheng, Shao-Kuan Lee, Hai-Ching Chen
  • Patent number: 9881871
    Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20180012761
    Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 11, 2018
    Inventors: Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee, Ming-Feng Shieh, Ru-Gun Liu, Shau-Lin Shue, Tien-I Bao, Tsai-Sheng Gau, Yung-Hsu Wu
  • Patent number: 9859154
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The dielectric layer has a protection region and a lower portion that is between the protection region and the semiconductor substrate. The protection region contains more carbon than the dielectric layer. The semiconductor device structure also includes a conductive feature penetrating through the protection region, and a lower portion of the conductive feature is surrounded by the lower portion of the dielectric layer.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Kuan Lee, Hsin-Yen Huang, Hai-Ching Chen
  • Patent number: 9859152
    Abstract: A method for forming a protecting layer includes determining an expected concentration of metal ions in a dielectric layer. The method also includes determining a thickness of the protecting layer based on the expected concentration of metal ions. The method also includes forming the protecting layer at the determined thickness and in contact with the dielectric layer. The protecting layer can include at least one of silicon doped nitride, carbon nitride, silicon nitride, or silicon carbon.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
  • Patent number: 9852915
    Abstract: A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration. Then, based upon such measurement, a makeup amount of the components may be added be a makeup unit to the etching solution to control the concentration of the components within the etching system.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: December 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu Lee, Ying-Hao Kuo, Hai-Ching Chen, Tien-I Bao