Patents by Inventor Hai-Ching Chen

Hai-Ching Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9281263
    Abstract: Some embodiments of the present disclosure relate to an interconnect structure for connecting devices of a semiconductor substrate. The interconnect structure includes a dielectric layer over the substrate and a continuous conductive body passing through the dielectric layer. The continuous conductive body is made up of a lower body region and an upper body region. The lower body region has a first width defined between opposing lower sidewalls of the continuous conductive body, and the upper body region has a second width defined between opposing upper sidewalls of the continuous conductive body. The second width is less than the first width. A barrier layer separates the continuous conductive body from the dielectric layer.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming Han Lee, Hai-Ching Chen, Hsiang-Huan Lee, Tien-I Bao, Chi-Lin Teng
  • Patent number: 9275953
    Abstract: A semiconductor integrated circuit (IC) with a dielectric matrix is disclosed. The dielectric matrix is located between two conductive features. The matrix includes a first nano-scale dielectric block, a second nano-scale dielectric block, and a first nano-air-gap formed by a space between the first nano-scale dielectric block and the second nano-scale dielectric block. The matrix also includes third nano-scale dielectric block and a second nano-air-gap formed by a space between the second nano-scale dielectric block and the third nano-scale dielectric block. The nano-scale dielectric blocks share a first common width, and the nano-air-gaps share a second common width. An interconnect structure integrates the dielectric matrix with the conductive features.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yen Huang, Yu-Sheng Chang, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20160035571
    Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.
    Type: Application
    Filed: October 7, 2015
    Publication date: February 4, 2016
    Inventors: Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee, Ming-Feng Shieh, Ru-Gun Liu, Shau-Lin Shue, Tien-I Bao, Tsai-Sheng Gau, Yung-Hsu Wu
  • Patent number: 9230911
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature and a second conductive feature in the LK dielectric layer; a first spacer along a first sidewall of the first conductive feature; a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature; an air gap between the first spacer and the second spacer; and a third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Tien-I Bao, Shau-Lin Shue
  • Publication number: 20150380321
    Abstract: A method for fabricating a semiconductor structure includes providing a substrate and a first layer over the substrate, wherein the first layer includes one or more overlay marks. The method further includes forming one or more layers on the first layer and performing a dark field (DF) inspection on the one or more overlay marks underlying the one or more layers to receive a post-film-formation data.
    Type: Application
    Filed: September 10, 2015
    Publication date: December 31, 2015
    Inventors: Bo-Jiun Lin, Hai-Ching Chen, Hsin-Chieh Yao, Tien-I Bao
  • Patent number: 9224643
    Abstract: The present disclosure provides one embodiment of a method to form an interconnect structure. The method includes forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills in the plurality of vias; and etching the metal layer such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal lines, aligned with plurality of vias, respectively.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ju Lee, Tien-I Bao, Ming-Shih Yeh, Hai-Ching Chen, Shau-Lin Shue
  • Publication number: 20150371953
    Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.
    Type: Application
    Filed: August 31, 2015
    Publication date: December 24, 2015
    Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
  • Patent number: 9177797
    Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: November 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Chang, Chung-Ju Lee, Cheng-Hsiung Tsai, Yung-Hsu Wu, Hsiang-Huan Lee, Hai-Ching Chen, Ming-Feng Shieh, Tien-I Bao, Ru-Gun Liu, Tsai-Sheng Gau, Shau-Lin Shue
  • Patent number: 9165822
    Abstract: A semiconductor device structure and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method comprising forming a first conductive line over a substrate, and conformally forming a first dielectric layer over a top surface and a sidewall of the first conductive line, the first dielectric layer having a first porosity percentage and a first carbon concentration. The method further comprises forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a second porosity percentage and a second carbon concentration, the second porosity percentage being different from the first porosity percentage, and the second carbon concentration being less than the first carbon concentration.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yen Huang, Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
  • Patent number: 9134633
    Abstract: The present disclosure provides a method for fabricating a semiconductor structure. The method comprises providing a substrate and a patterned layer formed on the substrate, one or more overlay marks being formed on the patterned layer; performing a pre-film-formation overlay inspection using a bright field (BF) inspection tool to receive a pre-film-formation data on the one or more overlay marks on the patterned layer; forming one or more layers on the patterned layer; performing a post-film-formation overlay inspection using a dark field (DF) inspection tool to receive a post-film-formation data on the one or more overlay marks underlying the one or more layers; and determining whether the pre-film-formation data matches the post-film-formation data.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jiun Lin, Hsin-Chieh Yao, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20150253500
    Abstract: A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.
    Type: Application
    Filed: May 18, 2015
    Publication date: September 10, 2015
    Inventors: Chun-Hao Tseng, Wan-Yu Lee, Hai-Ching Chen, Tien-l Bao
  • Patent number: 9129968
    Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20150212270
    Abstract: A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer.
    Type: Application
    Filed: April 9, 2015
    Publication date: July 30, 2015
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20150197849
    Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.
    Type: Application
    Filed: January 13, 2014
    Publication date: July 16, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiang-Huan Lee, Shau-Lin Shue, Keith Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang, Chung-En Kao, Ming-Han Lee, Hsin-Yen Huang
  • Publication number: 20150187696
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature and a second conductive feature in the LK dielectric layer; a first spacer along a first sidewall of the first conductive feature; a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature; an air gap between the first spacer and the second spacer; and a third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 2, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Tien-I Bao, Shau-Lin Shue
  • Publication number: 20150179532
    Abstract: The present disclosure provides a method for fabricating a semiconductor structure. The method comprises providing a substrate and a patterned layer formed on the substrate, one or more overlay marks being formed on the patterned layer; performing a pre-film-formation overlay inspection using a bright field (BF) inspection tool to receive a pre-film-formation data on the one or more overlay marks on the patterned layer; forming one or more layers on the patterned layer; performing a post-film-formation overlay inspection using a dark field (DF) inspection tool to receive a post-film-formation data on the one or more overlay marks underlying the one or more layers; and determining whether the pre-film-formation data matches the post-film-formation data.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 25, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jiun Lin, Hsin-Chieh Yao, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20150168659
    Abstract: An embodiment is a semiconductor device comprising an optical device over a first substrate, a vertical waveguide on a top surface of the optical device, the vertical waveguide having a first refractive index, and a capping layer over the vertical waveguide, the capping layer configured to be a lens for the vertical waveguide and the capping layer having a second refractive index.
    Type: Application
    Filed: February 26, 2015
    Publication date: June 18, 2015
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20150155171
    Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 4, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Sheng Chang, Chung-Ju Lee, Cheng-Hsiung Tsai, Yung-Hsu Wu, Hsiang-Huan Lee, Hai-Ching Chen, Ming-Feng Shieh, Tien-I Bao, Ru-Gun Liu, Tsai-Sheng Gau, Shau-Lin Shue
  • Patent number: 9041015
    Abstract: A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo, Hai-Ching Chen, Tien-I Bao
  • Patent number: 9036956
    Abstract: A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: May 19, 2015
    Assignee: Haynes and Boone, LLP
    Inventors: Chun-Hao Tseng, Wan-Yu Lee, Hai-Ching Chen, Tien-I Bao