Abstract: A memory device includes a transistor device; a memory cell electrically coupled to a source or drain of the transistor device, wherein the memory cell includes an FJT structure; and a heating structure formed around the memory cell on a plurality of sides. The FJT structure includes a first conductive electrode having sidewalls that extend in a vertical direction to a first elevation level, a second conductive electrode having sidewalls that extend in the vertical direction to the first elevation level, and a switching barrier disposed between the first conductive electrode and the second conductive electrode and having sidewalls that extend in the vertical direction to the first elevation level, wherein the vertically extending sidewalls of the first conductive electrode, the second conductive electrode, and the switching barrier terminate at the first elevation level. The switching barrier includes ferroelectric (Fe) material that may be polarized to store information.

Abstract: A pyroelectric generator may be included in the same semiconductor device as a radio frequency (RF) switch (e.g., a phase-change material (PCM) RF switch and/or other types of RF switch). The pyroelectric generator includes a pyroelectric material layer between two electrodes. The pyroelectric generator is configured to scavenge thermal energy that is generated during the operation of the RF switch, and to convert the thermal energy into electrical energy that may be stored and reused.

Abstract: Valleytronic devices comprise a channel layer having ferrovalley properties—band-spin splitting and Berry curvature dependence on the polarization of the channel layer. Certain monochalcogenides possess these ferrovalley properties. Valleytronic devices utilize ferrovalley properties to store and/or carry information. Valleytronic devices can comprise a cross geometry comprising a longitudinal portion and a transverse portion. A spin-polarized charge current injected into the longitudinal portion of the device is converted into a voltage output across the transverse portion via the inverse spin-valley Hall effect whereby charge carriers acquire an anomalous velocity in proportion to the Berry curvature and an applied in-plane electric field resulting from an applied input voltage. Due to the Berry curvature dependency on the material polarization, switching the polarity of the input voltage that switches the channel layer polarization also switches the polarity of the differential output voltage.

Abstract: A Nickel-based alloy includes (in wt %): 25.7%-27.3% Cobalt (Co), 15.0%-16.0% Chromium (Cr), 12.2%-13.2% Aluminum (Al), 0.3%-0.5% Yttrium (Y), 2.5%-3.5% Ruthenium (Ru), 0.4%-0.8% Silicon (Si), 0.4%-0.6% Tantalum (Ta), and 0.4%-0.6% Molybdenum (Mo).

Abstract: A Nickel-based alloy which includes (in wt %): Cobalt (Co) 27.0%-29.0%; Chrome (Cr) 16.0%-18.0%; Aluminum (Al) 11.6%-12.6%; Yttrium (Y) 0.3%-0.5%; Iron (Fe) 4.0%-5.0%; optionally Tantalum (Ta) 0.6%-0.8%; Molybdenum (Mo) 0.4%-0.6%; Silicon (Si) 0.4%-0.6%; and the rest Nickel (Ni).

Abstract: Technologies for a transistor with a ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a ferroelectric gate dielectric that is lattice matched to the channel of the transistor. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one transistor memory cell.

Abstract: A semiconductor structure may include semiconductor devices located on a substrate, metal interconnect structures that are located within dielectric material layers overlying the semiconductor devices and are electrically connected to the semiconductor devices, and an energy harvesting device located over the metal interconnect structures and comprising a Schottky barrier diode, a first diode electrode located on a first side of the Schottky barrier diode, and a second diode electrode connected to a second side of the Schottky barrier diode

Abstract: In one embodiment, an integrated circuit apparatus includes a plurality of metallization layers, each metallization layer comprising voltage supply lines and signal lines. The apparatus also includes logic circuits formed between respective pairs of metallization layers, with each logic circuit comprising non-CMOS logic devices to perform an operation on a respective bit of an input set of bits. The non-CMOS logic devices may include one or more of ferroelectric field-effect transistor (FeFET) devices or spintronic logic devices (e.g., magnetoelectric spin orbit (MESO) devices or ferroelectric spin orbit logic (FSOL) devices), and each logic circuit may be formed on a different vertical plane within the apparatus.

Abstract: A gas turbine blade including a root for connecting to a rotor of a gas turbine, a platform attached to the root defining a side surface and a groove formed in the side surface, and an airfoil including a metallic substrate extending from a surface of the platform to a tip, the airfoil including a pressure side and a suction side meeting at a trailing edge and a leading edge, and a platform impingement plate. The platform impingement plate includes a circumferential edge surrounding a cavity, the edge positioned to contact the platform, a plate surface positioned to from the cavity between the first surface and the plate surface, and a flat member having a face attached to the plate surface and at least one end portion. A gas turbine blade including a platform sealing wire positioned in a groove of the platform is also provided.

Abstract: Technologies for majority gates are disclosed. In one embodiment, a ferroelectric layer has three inputs and an output adjacent a surface of the ferroelectric. When a voltage is applied to each input, the inputs and a ground plane below the ferroelectric layer form a capacitor. The ferroelectric layer becomes polarized based on the applied voltages at the inputs. The portion of the ferroelectric layer near the output becomes polarized in the direction of polarization of the majority of the inputs. The output voltage then reflects the majority voltage of the inputs.

Abstract: In one embodiment, an integrated circuit die includes: a first layer comprising a magnetoelectric material; a second layer comprising a monolayer transition metal dichalcogenide (TMD); a magnet between the first layer and the second layer, wherein the magnet has perpendicular magnetic anisotropy; a first conductive trace coupled to the first layer; and a second conductive trace coupled to the magnet.

Abstract: In one embodiment, a first integrated circuit component, a second integrated circuit component, and an electrical interconnect coupling the first integrated circuit component and the second integrated circuit component. The interconnect comprises one or more spintronic logic devices.

Abstract: A spin orbit logic device includes: a first electrically conductive layer; a layer including a magnetoelectric material (ME layer) on the first electrically conductive layer; a layer including a ferromagnetic material with in-plane magnetic anisotropy (FM layer) on the ME layer; a second electrically conductive layer on the FM layer; a layer including a dielectric material on the second electrically conductive layer (coupling layer); a layer including a spin orbit coupling material (SOC layer) on the coupling layer; and a layer including a ferromagnetic material with perpendicular magnetic anisotropy (PMA layer) on the SOC layer.

Abstract: A control test system of the hydrogen internal combustion engine vehicle microcomputer includes a hydrogen treatment unit; the hydrogen treatment unit includes a detection box; an absorption box, an impurity removal box, a purification box and a water storage tank are arranged on an outer wall of the detection box; a first spring is fixedly mounted on an upper wall of an inner cavity of the absorption box; a lower end of the first spring is fixedly connected with a piston plate which is in sliding connection with an inner wall of the absorption box; amounting cylinder is arranged on an upper wall of an inner cavity of the purification box; and a plurality of adsorption rods are arranged on an outer wall of the mounting cylinder in an annular array mode.

Abstract: The present application relates to a pet safety management method and system, computer equipment and a storage medium. The method includes: acquiring a first video comprising a target pet and a target object, the target object being an active object except the target pet; analyzing the first video to determine a first state of the target pet and a second state of the target object; acquiring a surrounding environment video of the target pet if the target pet is determined to be in an initial dangerous state according to the first state and the second state; and analyzing the surrounding environment, determining that the target pet is in a dangerous state if the surrounding environment is an interference-free environment, and controlling an warning device carried by the target pet to send a warning message to timely prevent a pet from being stolen.

Abstract: A cracking process for a reaction distillation of chlorosilane slurry includes feeding a chlorosilane slurry into a phase separator, drying a solid phase, feeding a chlorosilane polymer into a plate distillation column, returning kettle materials of the plate distillation column, and dividing a material produced from a top of the column. The process adopts an ionic liquid catalyst, which is environmentally friendly and reusable. The cracking and distillation of chlorosilane polymer are carried out simultaneously to shorten the time and increase the utilization rate of raw materials, which can reduce energy consumption and save costs and facilitate industrial production. A plate column is used as a distillation column, in which the two phases of the gas and liquid are sufficiently contacted. Therefore, the transfer of mass and heat is good, the production capacity is good, and the tower is not easily blocked, thereby making it easy to clean.

Abstract: A first type of ferroelectric capacitor comprises electrodes and an insulating layer comprising ferroelectric oxides. In some embodiments, the electrodes and the insulating layer comprise perovskite ferroelectric oxides. A second type of ferroelectric capacitor comprises a ferroelectric insulating layer comprising certain monochalcogenides. Both types of ferroelectric capacitors can have a coercive voltage that is less than one volt. Such capacitors are attractive for use in low-voltage non-volatile embedded memories for next-generation semiconductor manufacturing technologies.

Abstract: A probabilistic bit (p-bit) comprises a magnetic tunnel junction (MTJ) comprising a free layer whose magnetization orientation randomly fluctuates in the presence of thermal noise. The p-bit MTJ comprises a reference layer, a free layer, and an insulating layer between the reference and free layers. The reference layer and the free layer comprise synthetic antiferromagnets. The use of a synthetic antiferromagnet for the reference layer reduces the amount of stray magnetic field that can impact the magnetization of the free layer and the use of a synthetic antiferromagnet for the free layer reduces stray magnetic field bias on p-bit random number generation. Tuning the thickness of the nonmagnetic layer of synthetic antiferromagnet free layer can result in faster random number generation time relative to a comparable MTJ with a free layer comprising a single-layer ferromagnet.

Abstract: Provided is a system for measuring gas temperature and component concentrations in a combustion field based on optical comb. The system includes two pulse laser devices, two continuous laser devices, a beam splitting device, a measurement path, an interference signal detecting device, an optical processing and electrical processing device and a signal acquisition and analysis device. The measurement path refers to the combustion field to be measured. The interference signal detecting device outputs an interference signal. The optical processing and electrical processing device includes several optic elements and electrical elements, and outputs an adaptive compensation signal and an asynchronous sampling clock signal after a series of processing on output of the two pulse laser devices and two continuous laser devices. The signal acquisition and analysis device outputs the measurement result based on the adaptive compensation signal, the asynchronous sampling clock signal and a stable interference signal.

Abstract: The present disclosure provides a GPU-based third-order low-rank tensor calculation method. Operation steps of the method include: transmitting, by a CPU, third-order real value tensor input data DATA1 to a CPU; performing, by the GPU, Fourier transforms on the DATA1, to obtain third-order complex value tensor data DATA2; performing, by the GPU, matrix operations on the DATA2, to obtain third-order complex value tensor data DATA3; performing, by the GPU, inverse Fourier transforms on the DATA3, to obtain third-order real value tensor output data DATA4; and transmitting, by the GPU, the DATA4 to the CPU. In the present disclosure, in the third-order low-rank tensor calculation, a computational task with high concurrent processes is accelerated by using the CPU to improve computational efficiency. Compared with conventional CPU-based third-order low-rank tensor calculation, computational efficiency is significantly improved, and same calculation can be completed by using less time.