Abstract: A display panel and a display device are provided. The display panel includes: a display region; a peripheral region surrounding the display region; a plurality of pixel units, located in the display region and configured to display an image; a plurality of data lines, electrically connected with the plurality of pixel units and configured to input data signals to the plurality of pixel units; a plurality of data transmission lines, located in the peripheral region and connected with the plurality of data lines; and at least two repair structures, wherein each of the at least two repair structures includes a first repair line and a second repair line, the first repair line is overlapped with the plurality of data transmission lines, and the second repair line is overlapped with the plurality of data lines.

Abstract: A display panel is disclosed. The display panel includes a base substrate; and an active layer arranged on a side of the base substrate. The active layer includes: a sixth active portion, a seventh active portion, a tenth active portion and a second initialization signal line, the second initialization signal line is connected to an end of the seventh active portion away from the sixth active portion, the second initialization signal line is used for providing an initialization signal to a seventh transistor, the seventh transistor comprises the seventh active portion, and the second initialization signal line extends along a first direction.

Abstract: A display substrate and a manufacturing method therefor, and a display device are provided. The display substrate includes a drive circuit layer disposed on a substrate, the drive circuit layer includes a plurality of circuit units, at least one circuit unit includes a pixel drive circuit, a first power supply line providing a power supply signal to the pixel drive circuit, a data signal line providing a data signal to the pixel drive circuit, and a data fan-out line connected with the data signal line; at least a portion of the first power supply line, the data signal line, and the data fan-out line extends along a second direction and is arranged at intervals along a first direction, at least a portion of the data fan-out line is disposed between the first power supply line and the data signal line, the first direction intersects with the second direction.

Abstract: An array substrate is provided. The array substrate includes a plurality of first subpixels in a first region and a plurality of second subpixels in a second region. The plurality of first subpixels include a plurality of first pixel driving circuits. The plurality of second subpixels include a plurality of second pixel driving circuits. A respective first pixel driving circuit of the plurality of first pixel driving circuits includes a smaller number of transistors than a respective second pixel driving circuit of the plurality of second pixel driving circuits. The first region has a light transmittance higher than the second region, and a subpixel density same as the second region.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes sub-pixels, a pixel defining pattern, and a defining structure. The sub-pixel includes a light-emitting functional layer. The pixel defining pattern includes first openings and second openings, a portion in the defining structure exposed by the second opening is configured to isolate the light-emitting functional layer. The sub-pixels include a first sub-pixel and a second sub-pixel, a turn-on voltage of the first sub-pixel is higher than that of the second sub-pixel; the defining structure includes a first defining structure surrounding the second sub-pixel and a second defining structure surrounding the second sub-pixel; the first defining structure is not exposed by the second opening; or a proportion of the first defining structure exposed by the second opening is less than a proportion of the second defining structure exposed by the second opening.

Abstract: A shift register and a driving method thereof, a gate driving circuit, and a display device are provided. The shift register includes: an input circuit configured to input an input voltage to a first node under control of a first clock signal; a first control circuit configured to output a first control signal to a first output node under control of the first clock signal, a voltage of the first node, and a second clock signal; a second control circuit configured to output a second control signal to the second output node under control of the voltage of the first node; and an output circuit configured to write a first voltage signal or a second voltage signal into a first output terminal as a first output signal under control of the first control signal and the second control signal.

Abstract: Provided are a display substrate, a driving method thereof, and a display apparatus. The display substrate includes multiple sub-pixels, a sub-pixel includes a pixel drive circuit and a light emitting device, the pixel drive circuit includes an initial signal line (INIT), a reset signal line (Reset) and multiple transistors, the initial signal line includes a first branch (INIT-1). Multiple transistors include a drive transistor, a first reset transistor and a second reset transistor, the drive transistor provides a drive current to the light emitting device, the first reset transistor resets a gate of the drive transistor through the INIT-1 under control of the reset signal line. The second reset transistor resets a first terminal of the light emitting device through the INIT-1 under control of the reset signal line. The first reset transistor and the second reset transistor in a same sub-pixel are controlled by a same reset signal line.

Abstract: A display substrate, and a display apparatus corresponding thereto and a manufacturing method therefor. The display substrate comprises: a display region and a non-display region, wherein the non-display region is provided with a gate driving circuit, which comprises a plurality of cascaded shift register units. Each shift register unit comprises: an input circuit (10), a first control circuit (11), a second control circuit (12) and an output circuit (15), wherein the first control circuit (11) is located between the input circuit (10) and the output circuit (15) in a first direction, and the first control circuit (11) is arranged in the first direction; and the second control circuit (12) is adjacent to the first control circuit (11) in a second direction; the first direction intersects with the second direction.

Abstract: There is provided a pixel driving circuit and method and a display panel. The pixel driving circuit includes a driving circuit, a control circuit, a voltage stabilization circuit, and a first storage circuit. The driving circuit is configured to provide a driving current to a third node according to a signal from a first node. The control circuit is configured to create conduction between second and fourth nodes in response to a signal from a first enable signal terminal, and create conduction between the first power supply terminal and the fourth node in response to the signal from the first enable signal terminal. The voltage stabilization circuit configured to transmit a signal from the reference voltage terminal to the fourth node in response to a signal from the second enable signal terminal. The first storage circuit configured to store electric charges of the first and fourth nodes.

Abstract: A display substrate and a manufacturing method therefor, and a display device are provided in the present disclosure. The display substrate includes a drive circuit layer disposed on a substrate, the drive circuit layer includes a plurality of circuit units, at least one circuit unit of the plurality of circuit units includes a pixel drive circuit, a first power supply line providing a power supply signal to the pixel drive circuit, a data signal line providing a data signal to the pixel drive circuit, and a data fan-out line connected with the data signal line; at least a portion of the first power supply line, the data signal line, and the data fan-out line extends along a second direction and is arranged at intervals along a first direction.

Abstract: A display substrate and a display device. The display substrate includes a first sub-pixel and a third sub-pixel, the first sub-pixel includes a first data line pattern, and the third sub-pixel includes a third data line pattern; the first sub-pixel and the third sub-pixel both include a sixth transistor and an anode pattern; the second electrode of the sixth transistor is electrically connected to the corresponding anode pattern; the third sub-pixel further includes a fourth conductive connection portion, and the fourth conductive connection portion; in the third sub-pixel, an orthographic projection of the anode pattern on the substrate at least partially overlaps an orthographic projection of the third data line pattern on the substrate, and at least partially overlaps an orthographic projection of the first data line pattern adjacent to the third data line pattern along the first direction on the substrate.

Abstract: A display panel and a display device are provided. The display panel includes a display area and a non-display area on a side of the display area. The non-display area includes a bending area, a bonding area, and a wiring area between the bending area and the bonding area. The display panel includes: a base substrate and a touch structure on the base substrate. The touch structure includes a touch lead led out from the display area and extending to the bonding area. The touch lead includes a first lead in the bending area and a second lead in the wiring area. The first lead and the second lead are electrically connected and located in different metal layers. The second lead is made of a single-layer metal wire.

Abstract: A display substrate is disclosed, including a display area and a non-display area. The non-display area has a gate drive circuit including multiple cascaded shift register units. A shift register unit includes an input control circuit and an output circuit. The input control circuit is electrically connected to a clock signal line group, a first power supply line, a second power supply line and an output circuit, the output circuit is electrically connected to the first power supply line and a second power supply line. The input control circuit at least includes an input circuit and a first control circuit. The clock signal line group, the second power supply line, the input control circuit, the output circuit and the first power supply line are arranged sequentially along a first direction. The input circuit is located between the second power supply line and the first control circuit in the first direction.

Abstract: A display panel and a display device are disclosed. The display panel includes display area and a peripheral area surrounding the display area. The peripheral area includes a first peripheral area located at a side of the display area, the first peripheral area has a cell test area for arranging a cell test unit, the display panel has a first edge, and the first edge is located at a side of the first peripheral area away from the display area. The display panel is provided with a reference power bus and a touch signal line, and in the first peripheral area, the reference power bus has a reference power bus protrusion.

Abstract: Provided is a display panel including: a substrate; a light-emitting device disposed in a display region; at least one signal wiring disposed in a non-display region, wherein the signal wiring is electrically connected to the light-emitting device, and the signal wiring includes at least two layers of sub-signal wirings, two adjacent layers of the sub-signal wirings being disposed in different layers and lapped with each other; and at least one auxiliary layer disposed in the non-display region, wherein the auxiliary layer is disposed between two adjacent layers of the sub-signal wirings, and the auxiliary layer includes a first via, the sub-signal wiring disposed on a side, proximal to the substrate, of the auxiliary layer being lapped with the sub-signal wiring disposed on a side, distal from the substrate, of the auxiliary layer by the first via.

Abstract: Provided are a display substrate and a display device. The display substrate includes a base substrate, and a driving circuit layer and a light-emitting device layer on the base substrate. The display substrate includes a light-transmitting display area and a normal display area, the normal display area surrounds at least a portion of the light-transmitting display area. The normal display area includes multiple normal driving circuits and multiple dummy driving circuits; some dummy driving circuit are used for driving light-emitting devices located in the light-transmitting display area. The display substrate further includes multiple normal data lines coupled to the normal driving circuits; at least one normal data line is coupled to a data signal input terminal through a data lead; an orthographic projection of the data lead onto the base substrate at least partially overlaps an orthographic projection of the dummy driving circuit onto the base substrate.

Abstract: Disclosed is a pixel circuit arranged in a display substrate, which comprises a first driving mode and a second driving mode. Content displayed in the display substrate comprises multiple display frames. In the first driving mode and the second driving mode, the display frames comprise refresh frames. A signal of a second scanning line is the same as that of a third scanning line. The time of which the signal of the second scanning line is an active level signal comprises a first refresh time period, a second refresh time period and a third refresh time period, which sequentially occur at intervals. During the second refresh time period, a signal of a first scanning line is an inactive level signal. The voltage of a signal at a reset voltage end is a positive voltage, and the voltage of a signal at a first initial voltage end is a negative voltage.

Abstract: A display substrate includes a substrate and a gate driving circuit provided on the substrate; the gate driving circuit includes: a frame start signal line, a clock signal line, an inverted clock signal line, a first level signal line, a second level signal line, and a plurality of shift register units. The plurality of transistors at least include a first transistor, a second transistor, and a third transistor, active layers of the first, second and third transistors are formed by a continuous first semiconductor layer, the first semiconductor layer extends along a first direction; the first semiconductor layer includes at least three channel portions corresponding to the first transistor, the second transistor and the third transistor, and a conductive portion provided between adjacent channel portions, transistors corresponding to the adjacent channel portions are coupled to each other through a corresponding conductive portion.

Abstract: A pixel circuit includes a data writing sub-circuit, a driving sub-circuit, and one or more potential maintenance sub-circuits. The data writing sub-circuit is coupled to at least a first voltage signal terminal, a data signal terminal, a first scan signal terminal and a first node, and writes a data signal provided by the data signal terminal into the first node under control of at least a first scan signal provided by the first scan signal terminal. The driving sub-circuit is coupled to the first node, a second node and a third node, and creates a path between the second node and the third node under control of a potential at the first node. A potential maintenance sub-circuit is coupled to a circuit node and a reference signal terminal, and maintains a potential at the circuit node through a reference signal provided by the reference signal terminal.

Abstract: A display substrate, and a display apparatus corresponding thereto and a manufacturing method therefor. The display substrate comprises: a display region and a non-display region, wherein the non-display region is provided with a gate driving circuit, which comprises a plurality of cascaded shift register units. Each shift register unit comprises: an input circuit (10), a first control circuit (11), a second control circuit (12) and an output circuit (15), wherein the first control circuit (11) is located between the input circuit (10) and the output circuit (15) in a first direction, and the first control circuit (11) is arranged in the first direction; and the second control circuit (12) is adjacent to the first control circuit (11) in a second direction; the first direction intersects with the second direction.