Abstract: Provided is a reverse-conducting IGBT chip including a first conductive type substrate; and several first conductive type short circuit regions arranged at intervals below the substrate and adjacent to a collector region. The short circuit regions are located outside a first preset range having the center of a chip as a center, in a second preset range outside the first preset range and having the center of the chip as a center, in a third preset range outside the second preset range and having the center of the chip as a center, and in a range outside the third preset range and enclosed by a chip edge.

Abstract: A cell structure of a silicon carbide MOSFET device, comprising a drift region (3) located on a substrate layer (2), a second conducting type well region (4) and a first JFET region (51) that are located in the drift region (3), an enhancement region located within a surface of the well region (4), a gate insulating layer (8) located on a first conducting type enhancement region (6), the well region (4) and the first JFET region (51) and being in contact therewith at the same time, a gate (9) located on the gate insulating layer, source metal (10) located on the enhancement region, Schottky metal (11) located on a second conducting type enhancement region (7) and the drift region (3), a second JFET region (52) located on a surface of the drift region (3) between the Schottky metals (11), and drain metal (12).

Abstract: Disclosed is a cellular structure of a silicon carbide MOSFET device, and a silicon carbide MOSFET device. The cellular structure comprises: second conductive well regions located on two sides of the cellular structure and arranged within the surface of a drift layer, first conductive source regions located within the surfaces of the well regions, and a gate structure located at the center of the cellular structure and in contact with the source regions, the well regions, and the drift layer. The cellular structure further comprises a source metal layer located above the source regions and forming ohmic contact with the source regions; on two sides of the cellular structure, side trenches are formed downwardly on regions of the drift layer that are not covered by the well regions; Schottky metal layers forming Schottky contact with the drift layer below the side trenches are arranged in the side trenches.

Abstract: We herein describe a semiconductor device sub-assembly comprising at least two power semiconductor devices and a contact of a first type. A first power semiconductor device is located on a first side of the contact of a first type, and a second power semiconductor device is located on a second side of the contact of a first type, where the second side is opposite to the first side.

Abstract: A disclosed DFE selection element reduces the degree of unrolling that might otherwise be required. In one illustrative embodiment of a method for converting a receive signal from a communication channel into a sequence of symbol decisions, the method includes, for each sampling interval: (a) generating a set of tentative symbol decisions each having a thermometer-coded representation with a least significant bit and a most significant bit; (b) providing each least significant bit as a thermometer-coded input to a first multiplexer; (c) providing each most significant bit as a thermometer-coded input to a second multiplexer; (d) applying a thermometer-coded representation of a preceding output symbol decision as selection inputs to the first and second multiplexers; and (e) capturing a current output symbol decision having a thermometer-coded representation that includes outputs of the first and second multiplexer.

Abstract: A disclosed DFE selection element reduces the degree of unrolling that might otherwise be required. In one illustrative embodiment of a method for converting a receive signal from a communication channel into a sequence of symbol decisions, the method includes, for each sampling interval: (a) generating a set of tentative symbol decisions each having a thermometer-coded representation with a least significant bit and a most significant bit; (b) providing each least significant bit as a thermometer-coded input to a first multiplexer; (c) providing each most significant bit as a thermometer-coded input to a second multiplexer; (d) applying a thermometer-coded representation of a preceding output symbol decision as selection inputs to the first and second multiplexers; and (e) capturing a current output symbol decision having a thermometer-coded representation that includes outputs of the first and second multiplexer.

Abstract: Provided are an insulated gate bipolar transistor and a preparation method therefor. An auxiliary groove gate, namely a structure of an auxiliary groove, an auxiliary gate layer and the corresponding gate oxide layer, is arranged below an emitting metal electrode between a first common groove and a second common groove so as to provide a carrier pathway when the insulated gate bipolar transistor is turned off, so that not only the turn-off speed of the insulated gate bipolar transistor is increased, but also the reverse-biased safety operation area characteristic of the insulated gate bipolar transistor is improved, thus improving the performance of the insulated gate bipolar transistor.

Abstract: A linear feedback equalizer includes comparators that digitize incoming analog signals. The equalizer further includes digital-to-analog converters (“DACs”) that transform a current digitized signal into one or more feedback analog signals. The equalizer further includes a subtractor that subtracts the feedback analog signals from the output of a continuous-time linear equalizer (“CTLE”) and provides the difference to the comparators as incoming analog signals.

Abstract: A reverse conducting IGBT device and a method for manufacturing the reverse conducting IGBT device are provided. The method includes: forming, based on a semiconductor structure including an IGBT cell region and a fast recovery diode cell region which are separated from each other, a copper electrode layer on an upper surface of the IGBT cell region; performing ion implantation on the semiconductor structure by using the copper electrode layer as a barrier layer, for controlling minority carrier lifetime of the fast recovery diode cell region; and forming a metal electrode layer on an upper surface of the fast recovery diode cell region, where the metal electrode layer is electrically connected to the copper electrode layer on the upper surface of the IGBT cell region.

Abstract: A linear feedback equalizer includes comparators that digitize incoming analog signals. The equalizer further includes digital-to-analog converters (“DACs”) that transform a current digitized signal into one or more feedback analog signals. The equalizer further includes a subtractor that subtracts the feedback analog signals from the output of a continuous-time linear equalizer (“CTLE”) and provides the difference to the comparators as incoming analog signals.

Abstract: High-data rate channel interface modules and equalization methods employing a finite impulse response (FIR) analog receive filter. Embodiments include an illustrative channel interface module having multiple amplifier-based delay units arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal; and a symbol decision element operating on the equalized signal to obtain a sequence of symbol decisions. An interface that extracts received data from the sequence of symbol decisions. The delay units may employ one or more delay cells each having a common-source amplifier stage followed by a source follower output stage, the two stages providing approximately equal portions of the propagation delay. An enhanced gate-to-drain capacitance in the common-source amplifier may increase propagation delay while reducing bandwidth limitations.

Abstract: A reverse conducting IGBT device and a method for manufacturing the reverse conducting IGBT device are provided. The method includes: forming, based on a semiconductor structure including an IGBT cell region and a fast recovery diode cell region which are separated from each other, a copper electrode layer on an upper surface of the IGBT cell region; performing ion implantation on the semiconductor structure by using the copper electrode layer as a barrier layer, for controlling minority carrier lifetime of the fast recovery diode cell region; and forming a metal electrode layer on an upper surface of the fast recovery diode cell region, where the metal electrode layer is electrically connected to the copper electrode layer on the upper surface of the IGBT cell region.

Abstract: High-data rate channel interface modules and equalization methods employing a finite impulse response (FIR) analog receive filter. Embodiments include an illustrative channel interface module having multiple amplifier-based delay units arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal; and a symbol decision element operating on the equalized signal to obtain a sequence of symbol decisions. An interface that extracts received data from the sequence of symbol decisions. The delay units may employ one or more delay cells each having a common-source amplifier stage followed by a source follower output stage, the two stages providing approximately equal portions of the propagation delay. An enhanced gate-to-drain capacitance in the common-source amplifier may increase propagation delay while reducing bandwidth limitations.

Abstract: Provided are an insulated gate bipolar transistor and a preparation method therefor. An auxiliary groove gate, namely a structure of an auxiliary groove, an auxiliary gate layer and the corresponding gate oxide layer, is arranged below an emitting metal electrode between a first common groove and a second common groove so as to provide a carrier pathway when the insulated gate bipolar transistor is turned off, so that not only the turn-off speed of the insulated gate bipolar transistor is increased, but also the reverse-biased safety operation area characteristic of the insulated gate bipolar transistor is improved, thus improving the performance of the insulated gate bipolar transistor.

Abstract: Disclosed is a trench gate IGBT. A dummy gate is arranged between two real gates. An emitter metal is in contact with the dummy gate, so that an emitter metal contact area is not limited to an area between trenches. The emitter metal contact area includes an area where the emitter metal is in contact with the dummy gate, thereby enlarging the emitter metal contact area, and accordingly reducing a distance between each of the real gates and the dummy gate. Consequently, the distance between each of the real gates and the dummy gate is no longer affected by a minimum emitter contact area, and a turn-on voltage drop of the trench gate IGBT can be greatly reduced.