Patents by Inventor Haim Granot

Haim Granot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10936041
    Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Alexander Gendler, Igor Yanover, Gavri Berger, Edo Hachamo, Elkana Korem, Hanan Shomroni, Daniela Kaufman, Lev Makovsky, Haim Granot
  • Publication number: 20200310511
    Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Alexander Gendler, Igor Yanover, Gavri Berger, Edo Hachamo, Elkana Korem, Hanan Shomroni, Daniela Kaufman, Lev Makovsky, Haim Granot
  • Publication number: 20090291672
    Abstract: A system and method for receiving travel information such as flight information, directional guidance to airport gates and facilities, and interacting autonomously with service providers such as airlines and rental car companies without requiring human resources to receive the tickets or car keys. The system devices essentially provide an automatic chaperon which can initiate processes such as querying databases or provide navigation guidance without intervention, setup procedures or any prior knowledge on behalf of the user. It can also access secured databases for retrieving rental car reservation information for automatic rental car checkout, personal health files for emergency cases, flight check-in, connecting flight information and call for emergency staff alerting the staff automatically of the caller's location within the compound, as well as recent health history and condition.
    Type: Application
    Filed: November 13, 2008
    Publication date: November 26, 2009
    Inventors: Ron Treves, Dina Treves, David Treves, Benny Schwabsky, Haim Granot
  • Patent number: 7043625
    Abstract: The present invention is a system in which a multiplicity of diverse dedicated hardware off-core execution units are connected to a core processor in order to increase the speed, power, and flexibility of the processor, and a method of operating the system. Reference instructions executed by the core processor initiate the execution of Configurable Long Instruction Word (CLIW) instructions stored in a CLIW memory. The operation of the off-core execution units is controlled by CLIW instructions. These CLIW instructions may also control operations performed by the core processor, and may be in addition to any other CLIW instructions that control the core processor exclusively. The off-core logic units are operationally connected to the data memory of the core processor under the control of the core processor's data address logic.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: May 9, 2006
    Assignee: Infineon Technologies AG
    Inventors: Eyal Rosin, Regis Hervigo, Haim Granot
  • Patent number: 6453407
    Abstract: A method for executing instructions in a data processor and improvements to data processor design, which combine the advantages of regular processor architecture and Very Long Instruction Word architecture to increase execution speed and ease of programming, while reducing power consumption. Instructions each consisting of a number of operations to be performed in parallel are defined by the programmer, and their corresponding execution unit controls are generated at compile time and loaded prior to program execution into a dedicated array in processor memory. Subsequently, the programmer invokes reference instructions to call these defined instructions, and passes parameters from regular instructions in program memory. As the regular instructions propogate down the processor's pipeline, they are replaced by the appropriate controls fetched from the dedicated array in processor memory, which then go directly to the execution unit for execution.
    Type: Grant
    Filed: February 10, 1999
    Date of Patent: September 17, 2002
    Assignee: Infineon Technologies AG
    Inventors: Yoav Lavi, Amnon Rom, Robert Knuth, Rivka Blum, Meny Yanni, Haim Granot, Anat Hershko, Georgiy Shenderovitch, Elliot Cohen, Eran Weingatren
  • Patent number: 6411978
    Abstract: A processor for performing a block floating point Fast Fourier Transform having improved signal to quantization noise ratio performance. In the radix-2 Decimation In Time algorithm, overflow between stages is prevented by a scale down by two invoked by comparison with a fixed comparison constant. Unfortunately, the fixed comparison constant is not always optimum for maximizing the signal to quantization noise ratio, which is degraded by excessive scale down. Moreover, current mechanisms are limited to the radix-2 block floating point FFT. The processor of the present invention provides the programmer with a FFT compare register which is loadable under program control, thus allowing the programmer to adjust the threshold at which scale down of the stage output is activated for better control over the signal to quantization noise ratio. In addition, the present invention supports other FFT structures besides the radix-2 block floating point FFT.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: June 25, 2002
    Assignee: Infineon Technologies Ag I. Gr.
    Inventors: Gil Naveh, Eran Weingarten, Haim Granot
  • Publication number: 20010037441
    Abstract: The present invention is a system in which a multiplicity of diverse dedicated hardware off-core execution units are connected to a core processor in order to increase the speed, power, and flexibility of the processor, and a method of operating the system. Reference instructions executed by the core processor initiate the execution of Configurable Long Instruction Word (CLIW) instructions stored in a CLIW memory. The operation of the off-core execution units is controlled by CLIW instructions. These CLIW instructions may also control operations performed by the core processor, and may be in addition to any other CLIW instructions that control the core processor exclusively. The off-core logic units are operationally connected to the data memory of the core processor under the control of the core processor's data address logic.
    Type: Application
    Filed: March 16, 2001
    Publication date: November 1, 2001
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Eyal Rosin, Regis Hervigo, Haim Granot