Abstract: The disclosure discloses a method for defending control flow attacks. When a data processor gives a response to an interrupt routine, a return address and a binary key are input to an encryption circuit to be encrypted to obtain an encrypted return address, and the obtained encrypted return address is synchronously written into a stack of the data processor and an built-in register bank; when the response given to the interrupt routine by the data processor is finished, the encrypted return address is read from the tack of the data processor and the built-in register bank; afterwards, the two encrypted return addresses are decrypted by first and second decryption circuits respectively to obtain two decrypted return addresses; and the two decrypted return addresses are compared to draw a conclusion whether the data process suffers from a control flow attack, and data processor determines to continue or terminate the routine accordingly.

Abstract: The invention discloses a circuit aging detection sensor based on voltage comparison. A control circuit generates an aging voltage signal, a standard voltage signal and a reference voltage signal. The aging voltage signal passes through a first voltage-controlled oscillator to generate an aging frequency signal. The standard voltage signal passes through a second voltage-controlled oscillator to generate a standard frequency signal. The standard frequency signal and the aging frequency signal pass through an aging detection circuit to generate a frequency difference signal. A level signal generated by a serial data detector passes through a beat-frequency oscillator to generate a reset signal. A counter quantizes aging information, which is converted by a digital-analog converter into a quantized voltage signal. The quantized voltage signal is compared with the reference voltage signal by a voltage comparator, to generate a hopping signal at a voltage superposition node, and an aging signal is output.

Abstract: A domino full adder based on delayed gating positive feedback comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first inverter, a second inverter, a third inverter and a fourth inverter.

Abstract: A domino full adder based on delayed gating positive feedback comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first inverter, a second inverter, a third inverter and a fourth inverter.

Abstract: The invention discloses a circuit aging detection sensor based on voltage comparison. A control circuit generates an aging voltage signal, a standard voltage signal and a reference voltage signal. The aging voltage signal passes through a first voltage-controlled oscillator to generate an aging frequency signal. The standard voltage signal passes through a second voltage-controlled oscillator to generate a standard frequency signal. The standard frequency signal and the aging frequency signal pass through an aging detection circuit to generate a frequency difference signal. A level signal generated by a serial data detector passes through a beat-frequency oscillator to generate a reset signal. A counter quantizes aging information, which is converted by a digital-analog converter into a quantized voltage signal. The quantized voltage signal is compared with the reference voltage signal by a voltage comparator, to generate a hopping signal at a voltage superposition node, and an aging signal is output.

Abstract: The disclosure discloses a method for defending control flow attacks. When a data processor gives a response to an interrupt routine, a return address and a binary key are input to an encryption circuit to be encrypted to obtain an encrypted return address, and the obtained encrypted return address is synchronously written into a stack of the data processor and an built-in register bank; when the response given to the interrupt routine by the data processor is finished, the encrypted return address is read from the tack of the data processor and the built-in register bank; afterwards, the two encrypted return addresses are decrypted by first and second decryption circuits respectively to obtain two decrypted return addresses; and the two decrypted return addresses are compared to draw a conclusion whether the data process suffers from a control flow attack, and data processor determines to continue or terminate the routine accordingly.