Abstract: In a branch guess type central processing unit of the invention, for executing a branch instruction, a presignalling instruction for designating a branch address is prefetched by an address/prefetch control circuit before the branch instruction is read out from a macroinstruction memory. This presignalling instruction is decoded. The branch address is stored in advance in an A register, a B register, and a C register. A plurality of instructions stored at the locations represented by these addresses are stored in a first instruction register, a second instruction register and a stack before executing the branch instruction. When the branch instructions are executed, the control can be transferred to jumped locations without causing any hazard in the pipeline.

Abstract: An electronic computer is disclosed which includes microprogram memory in which a microinstruction is stored, a microaddress control unit for supplying an address to said memory and a register for holding a microinstruction read out of said microprogram memory, the contents of the microprogram memory are stored in the first section of the memory of the microprogram-testing apparatus. The second section of said memory is supplied with data for testing the microinstruction. While the microinstruction is executed, the microinstruction and test data are read out of said memory at the same time, and supplied to the error detector and trace control circuit. The microprogram-testing apparatus further comprises a function switching control circuit, which decides whether the error detector or trace control circuit should be enabled. Where the error detector is selected, then an error in the microprogram is detected.

Abstract: A computer which executes a program made up of a plurality of blocks comprises a program counter which designates an address of an instruction to be executed, first and second registers that stores entry addresses of first and second blocks respectively of the program, and a push down stack that stores an entry address of a third block of the program. The instruction designated by the program counter causes the reading out of data from a main memory device so as to read out the contents of one of the first, second or third blocks of the program from the main memory device for execution. The designated instruction causes the reading of one of the entry addresses stored in the first and second registers or the push down stack so as to load such entry address into the program counter to cause the readout of the program block.