Patents by Inventor Hajime Yamaguchi

Hajime Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9780220
    Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor transistor. The oxide semiconductor transistor includes a semiconductor layer including an oxide semiconductor, the semiconductor layer including a source region and a source electrode. The source electrode includes a source conductive layer including copper, a first tantalum-containing region provided between the source conductive layer and the source region, the first tantalum-containing region including tantalum, a first low nitrogen composition region provided between the first tantalum-containing region and the source region, the first low nitrogen composition region including Ta1?x1Nx1 (0<x1<0.5), and a first high nitrogen composition region provided between the first low nitrogen composition region and the source region, the first high nitrogen composition region including Ta1?x2Nx2 (0.5?x2<1).
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 3, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuya Maeda, Shintaro Nakano, Nobuyoshi Saito, Hajime Yamaguchi
  • Publication number: 20170255324
    Abstract: A card type device includes a base having flexibility and a display having flexibility arranged on the base. A first touch sensor arranged on a first surface of the base or the display, a second touch sensor arranged on a second surface of the base or the display, the second surface being on the opposite side of the first surface, and a control circuit connected to the first touch sensor and the second touch sensor may be further provided.
    Type: Application
    Filed: February 17, 2017
    Publication date: September 7, 2017
    Inventors: Shinichiro OKA, Hiroshi MIZUHASHI, Shinya IUCHI, Yoshitoshi KIDA, Shinichi TAKAYAMA, Takenori HIROTA, Yosuke HYODO, Takuma NISHINOHARA, Yasukazu KIMURA, Hajime YAMAGUCHI
  • Patent number: 9640718
    Abstract: According to one embodiment, a method for manufacturing a display element is disclosed. The method can include forming a peeling layer, forming a resin layer, forming a barrier layer, forming an interconnect layer, forming a display layer, and removing. The peeling layer is formed on a major surface of a base body. The major surface has first, second, and third regions. The peeling layer includes first, second, and third peeling portions. The resin layer is formed on the peeling layer. The resin layer includes first and second resin portions. The barrier layer is formed on the first, second, and third peeling portions. The interconnect layer is formed on the barrier layer. The display layer is formed on the interconnect layer. The first peeling portion is removed from the first resin portion and the second peeling portion is removed from the second resin portion.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: May 2, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Miura, Tatsunori Sakano, Tomomasa Ueda, Nobuyoshi Saito, Shintaro Nakano, Yuya Maeda, Hajime Yamaguchi
  • Patent number: 9614099
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including a first semiconductor portion and a second semiconductor portion being continuous with the first semiconductor portion, a first gate electrode, a second gate electrode, an insulating film. The first semiconductor portion includes a first portion, a second portion and a third portion provided between the first portion and the second portion. The second semiconductor portion includes a fourth portion separated from the first portion, a fifth portion separated from the second portion, and a sixth portion provided between the forth portion and the fifth portion. The first gate electrode is separated from the third portion. The second gate electrode is separated from the sixth portion. The insulating film is provided at a first position between the first gate electrode and the semiconductor layer and at a second position between the second gate electrode and the semiconductor layer.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: April 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shintaro Nakano, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Yuya Maeda, Masaki Atsuta, Hajime Yamaguchi
  • Publication number: 20170061910
    Abstract: According to one embodiment, a liquid display device includes a liquid crystal display panel provided with pixel which includes pixel electrode, and has gradation values that vary, a driver which drives the pixel electrode, and a processor which supplies, if the gradation value of the pixel varies, the driver with a correction image signal based on an addition image signal in which a voltage based on the gradation value and a compensation voltage are added. The compensation voltage is based on pixel capacitances prior to and subsequent to variation of the gradation value and a voltage subsequent to the variation of the gradation value.
    Type: Application
    Filed: August 18, 2016
    Publication date: March 2, 2017
    Inventors: Hajime YAMAGUCHI, Yasushi KAWATA, Akio MURAYAMA
  • Publication number: 20160378249
    Abstract: According to an embodiment, an input device includes the following elements. The flexible touch panel includes a sensor area. The touch position detector detects a touch position on the sensor area to generate a detection signal. The deformation position detector detects a deformation position where a deformation amount is not less than a threshold on the sensor area. The input rejection area determination unit determines, based on the deformation position, an input rejection area. The input signal generator fails to output the detection signal as an input signal if the touch position is detected in the input rejection area, and outputs the detection signal as an input signal if the touch position is detected in an area other than the input rejection area.
    Type: Application
    Filed: September 9, 2016
    Publication date: December 29, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kentaro MIURA, Hajime YAMAGUCHI, Tatsunori SAKANO, Tomomasa UEDA, Nobuyoshi SAITO, Shintaro NAKANO
  • Publication number: 20160372604
    Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor transistor. The oxide semiconductor transistor includes a semiconductor layer including an oxide semiconductor, the semiconductor layer including a source region and a source electrode. The source electrode includes a source conductive layer including copper, a first tantalum-containing region provided between the source conductive layer and the source region, the first tantalum-containing region including tantalum, a first low nitrogen composition region provided between the first tantalum-containing region and the source region, the first low nitrogen composition region including Ta1?x1Nx1 (0<x1<0.5), and a first high nitrogen composition region provided between the first low nitrogen composition region and the source region, the first high nitrogen composition region including Ta1?x2Nx2 (0.5?x2<1).
    Type: Application
    Filed: August 30, 2016
    Publication date: December 22, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuya MAEDA, Shintaro NAKANO, Nobuyoshi SAITO, Hajime YAMAGUCHI
  • Patent number: 9488842
    Abstract: According to one embodiment, a liquid crystal optical device includes first and second substrate units and a liquid crystal layer. The first substrate unit includes a first substrate having a first major surface, and a first electrode extending along a first direction. The second substrate unit includes a second substrate and a first opposing electrode. The liquid crystal layer is provided between the first substrate unit and the second substrate unit and includes a first portion provided on a side of the first substrate unit and a second portion provided on a side of the second substrate unit. The first portion has a vertical alignment. The second portion has a horizontal alignment. A long axis of liquid crystal molecules in the second portion aligns along a second direction perpendicular to the first direction.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: November 8, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuko Kizu, Shinichi Uehara, Ayako Takagi, Masako Kashiwagi, Machiko Ito, Masahiro Baba, Hajime Yamaguchi
  • Patent number: 9448446
    Abstract: A liquid crystal optical device of an embodiment includes: a first substrate unit; a second substrate unit; and a liquid crystal layer interposed between the first substrate unit and the second substrate unit. The liquid crystal molecules on a side of a first alignment layer of the first substrate unit is aligned perpendicularly to a first principal surface of the first substrate unit while the liquid crystal molecules on a side of a second alignment layer of the second substrate unit are aligned horizontally along a second direction. The opposing electrode includes: a first region and a second region, the first region has N first openings, and the second region includes M second openings, N being an integer of 0 or greater, M being an integer of 1 or greater, M being greater than N.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: September 20, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuko Kizu, Machiko Ito, Hajime Yamaguchi, Ayako Takagi, Shinichi Uehara
  • Patent number: 9412765
    Abstract: According to one embodiment, a thin film transistor includes: a substrate; a semiconductor layer; first and second insulating films; and gate, source and drain electrodes. The semiconductor layer is provided on the substrate. The semiconductor layer is made of an oxide having indium. The semiconductor layer has first and second regions and other region. The first insulating film covers a top face of the other region. The second insulating film covers at least a pair of side surfaces of the semiconductor layer. The second insulating film is formed under a condition different from that for the first insulating film. The gate electrode is provided on the first and second insulating films or below the semiconductor layer. The source and drain electrodes are provided on the first and second regions, respectively. The drain and source electrodes sandwich the pair of the side surfaces of the semiconductor layer.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: August 9, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomomasa Ueda, Shintaro Nakano, Nobuyoshi Saito, Kentaro Miura, Yujiro Hara, Hajime Yamaguchi
  • Patent number: 9324879
    Abstract: According to one embodiment, a thin film transistor includes a substrate, a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, a source electrode, and a drain electrode. The gate electrode is provided on a part of the substrate. The first insulating film covers the gate electrode. The oxide semiconductor film is provided on the gate electrode via the first insulating film. The second insulating film is provided on a part of the oxide semiconductor film. The source and drain electrodes are respectively connected to first and second portions of the oxide semiconductor film not covered with the second insulating film. The oxide semiconductor film includes an oxide semiconductor. Concentrations of hydrogen contained in the first and second insulating films are not less than 5×1020 atm/cm3, and not more than 1019 atm/cm3, respectively.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: April 26, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shintaro Nakano, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Hajime Yamaguchi
  • Patent number: 9293600
    Abstract: A semiconductor element includes a semiconductor layer, a first and a second conductive unit, a gate electrode, and a gate insulating film. The semiconductor layer includes a first portion, a second portion, and a third portion provided between the first portion and the second portion. The first conductive unit is electrically connected to the first portion. The second conductive unit is electrically connected to the second portion. The gate electrode is separated from the first conductive unit, the second conductive unit, and the third portion. The gate electrode opposes the third portion. The gate insulating film is provided between the third portion and the gate electrode. A concentration of nitrogen of the first portion is higher than a concentration of nitrogen of the third portion. A concentration of nitrogen of the second portion is higher than the concentration of nitrogen of the third portion.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: March 22, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shintaro Nakano, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Yuya Maeda, Masaki Atsuta, Hajime Yamaguchi
  • Patent number: 9224871
    Abstract: According to one embodiment, a thin film transistor includes a first insulating film, a gate electrode, a semiconductor layer, a gate insulator film, a second insulating film, a source electrode, a tunneling insulating portion, and a drain electrode. The semiconductor layer is provided between the gate electrode and the first insulating film, and includes an amorphous oxide. The gate insulator film is provided between the semiconductor layer and the gate electrode. The second insulating film is provided between the semiconductor layer and the first insulating film. The tunneling insulating portion is provided between the semiconductor layer and the source electrode, and between the semiconductor layer and the drain electrode, and between the first insulating film and the second insulating film. The tunneling insulating portion includes oxygen and at least one selected from aluminum and magnesium. A thickness of the tunneling insulating portion is 2 nanometers or less.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: December 29, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuya Maeda, Hajime Yamaguchi, Tomomasa Ueda, Kentaro Miura, Shintaro Nakano, Nobuyoshi Saito, Tatsunori Sakano
  • Publication number: 20150372147
    Abstract: According to one embodiment, a thin film transistor includes a substrate, a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, a source electrode, and a drain electrode. The gate electrode is provided on a part of the substrate. The first insulating film covers the gate electrode. The oxide semiconductor film is provided on the gate electrode via the first insulating film. The second insulating film is provided on a part of the oxide semiconductor film. The source and drain electrodes are respectively connected to first and second portions of the oxide semiconductor film not covered with the second insulating film. The oxide semiconductor film includes an oxide semiconductor. Concentrations of hydrogen contained in the first and second insulating films are not less than 5×1020 atm/cm3, and not more than 1019 atm/cm3, respectively.
    Type: Application
    Filed: August 27, 2015
    Publication date: December 24, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro NAKANO, Tomomasa UEDA, Kentaro MIURA, Nobuyoshi SAITO, Tatsunori SAKANO, Hajime YAMAGUCHI
  • Patent number: 9204554
    Abstract: According to one embodiment, a method is disclosed for manufacturing a display device. A film material layer is formed on a support substrate. A first heating process for the film material layer at a first temperature to form a film layer and a second heating process for a second region surrounding a first region at a second temperature higher than the first temperature are performed. The first region is provided in a central part of the film layer. A display layer is formed in the first region and a peripheral circuit section is formed at least in a part of the second region. A third heating process is performed for at least a part of the film layer at a third temperature higher than the second temperature. In addition, the film layer is peeled off from the support substrate.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: December 1, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Sakano, Kentaro Miura, Nobuyoshi Saito, Shintaro Nakano, Tomomasa Ueda, Hajime Yamaguchi
  • Patent number: 9184408
    Abstract: According to one embodiment, a display panel includes a substrate, a switching element, a pixel electrode, an organic light emitting layer, an opposite electrode, a detecting electrode, and an insulating layer. The substrate has a major surface. The switching element is provided on the major surface. The switching element includes a semiconductor layer. The pixel electrode is provided on the major surface. The pixel electrode is electrically connected to the switching element. The organic light emitting layer is provided on the pixel electrode. The opposite electrode is provided on the organic light emitting layer. The detecting electrode is provided between the substrate and at least a part of the pixel electrode. The detecting electrode includes at least one element included in the semiconductor layer. The insulating layer is provided between the pixel electrode and the detecting electrode.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuyoshi Saito, Tomomasa Ueda, Hajime Yamaguchi, Kentaro Miura, Shintaro Nakano, Tatsunori Sakano
  • Patent number: 9159836
    Abstract: According to one embodiment, a thin film transistor includes a substrate, a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, a source electrode, and a drain electrode. The gate electrode is provided on a part of the substrate. The first insulating film covers the gate electrode. The oxide semiconductor film is provided on the gate electrode via the first insulating film. The second insulating film is provided on a part of the oxide semiconductor film. The source and drain electrodes are respectively connected to first and second portions of the oxide semiconductor film not covered with the second insulating film. The oxide semiconductor film includes an oxide semiconductor. Concentrations of hydrogen contained in the first and second insulating films are not less than 5×1020 atm/cm3, and not more than 1019 atm/cm3, respectively.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: October 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shintaro Nakano, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Hajime Yamaguchi
  • Patent number: 9159747
    Abstract: According to one embodiment, a display device includes a substrate unit, a thin film transistor, a pixel electrode and a display layer. The substrate unit includes a substrate, a first insulating layer provided on the substrate, and a second insulating layer provided on the first insulating layer. The thin film transistor is provided on the substrate unit and includes a gate electrode provided on the second insulating layer, a semiconductor layer of an oxide separated from the gate electrode, a gate insulation layer provided between the gate electrode and the semiconductor layer, a first conductive portion, a second conductive portion, and a third insulating layer. The pixel electrode is connected to one selected from the first and second conductive portions. The display layer is configured to have a light emission or a change of optical characteristic occurring according to a charge supplied to the pixel electrode.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: October 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shintaro Nakano, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Yuya Maeda, Hajime Yamaguchi
  • Patent number: 9131633
    Abstract: A display device includes: a flexible first substrate; a flexible second substrate provided facing the first substrate; a display part; and a wiring substrate. The display part has a display component which is disposed between the first substrate and the second substrate. The display component produces at least one of an optical characteristic change and a light emission. The wiring substrate is connected to a connection pad provided on at least one of the first substrate and the second substrate. At least a portion of the wiring substrate is interposed between the first substrate and the second substrate outside the display part.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: September 8, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Miura, Hajime Yamaguchi, Masao Tanaka, Takashi Miyazaki
  • Patent number: 9029853
    Abstract: According to one embodiment, a display device includes a first insulating layer, a second insulating layer, a pixel electrode, a light emitting layer, an opposite electrode and a pixel circuit. The second insulating layer is provided on the first insulating layer. The pixel electrode is provided on the second insulating layer and light-transmissive. The light emitting layer is provided on the pixel electrode. The opposite electrode is provided on the light emitting layer. The circuit is provided between the first insulating layer and the second insulating layer, includes an interconnect supplied with a drive current, and is configured to supply the drive current to the pixel electrode. The circuit is connected to the pixel electrode. The interconnect has a first region overlaying the pixel electrode when projected onto a plane parallel to the first insulating layer. The interconnect has an opening in the first region.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: May 12, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuyoshi Saito, Tomomasa Ueda, Toshiya Yonehara, Hajime Yamaguchi, Kentaro Miura, Shintaro Nakano, Tatsunori Sakano