Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract: A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through the memory devices.

Abstract: A memory system architecture is provided in which a memory controller controls operations of memory devices in a serial interconnection configuration. The memory controller has an output serial interface for sending memory commands and an input serial interface for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, flash memory (e.g., NAND- and NOR-type flash memories). In an initialization phase, the memory devices are assigned with consecutive number addresses. The memory controller sends a target address and can recognize the type of the targeted memory device. A data path for the memory commands and the memory responses is provided by the interconnection.

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.

Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

Abstract: A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through he memory devices.

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) having associated device type information is serially interconnected. A serial input (SI) containing a device type (DT) and a device identifier (ID) is fed to one device of the serial interconnection. Upon a match between the fed DT matches the DT of the device, the fed ID is latched in a register of the device and an ID for another device is generated, which is then transferred to the next device in the serial interconnection. Otherwise, ID generation is skipped. These steps are performed in all devices. Thus, sequential IDs are generated for the different device types and also the total number of each device type is recognized. If the fed DT is “don't care”, sequential IDs are generated for all devices and the total number of the devices is recognized.

Abstract: A dynamic random access memory (DRAM) device having memory cells is operated in a self-refresh mode and a normal mode. A mode detector provides a self-refresh mode signal in the self-refresh mode of operation. It includes a free-running oscillator for generating an oscillation signal independent of the self-refresh mode signal. In response to the oscillation signal, a self-request controller provides a self-refresh request signal in the self-refresh mode. The self-refresh signal is asynchoronized with the self-fresh mode signal and is provided to an address circuit to select a wordline for refreshing the memory cells thereof. The self-refresh request controller includes logic circuitry for arbitrating timing between initial active edges of the oscillation signal and the self-refresh mode signal and providing the self-refresh request and ceasing it, regardless of conflict between the self-refresh mode signal and the oscillation signal upon self-refresh mode entry and exit.

Abstract: A bridge device architecture for connecting discrete memory devices. The bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device includes a local control interface for connecting to the at least one discrete memory device, a local input/output interface for connecting to the at least one discrete memory device, and a global input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.

Abstract: A non-volatile semiconductor memory device, which comprises (i) an interface having an input for receiving an input clock and a set of data lines for receiving commands issued by a controller including an erase command; (ii) a module having circuit components in a feedback loop configuration and being driven by a reference clock; (iii) a clock control circuit capable of controllably switching between a first state in which the reference clock tracks the input clock and a second state in which the reference clock is decoupled from the input clock; and (iv) a command processing unit configured to recognize the commands and to cause the clock control circuit to switch from the first state to the second state in response to recognizing the erase command. The module consumes less power when the reference clock is decoupled from the input clock than when the reference clock tracks the input clock.

Abstract: A non-volatile semiconductor memory device, comprising: an interface for receiving commands issued by a controller, the commands including an erase command; a functional entity with circuit components and having a terminal; a node; switchable circuitry capable of controllably switching between a first operational state in which the terminal is electrically connected to the node and a second operational state in which the terminal is electrically decoupled from the node, the node being configured to have a signal for the functional entity communicated through it when the switchable circuitry is in the first operational state; and a command processing unit configured to recognize the commands issued by the controller and, in response to recognizing the erase command, to cause the switchable circuitry to switch from the first operational state to the second operational state.

Abstract: Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.

Abstract: A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes.

Abstract: A method or apparatus operates a multitude of devices in a serial interconnection configuration to establish a device identifier (ID) for each device. An input signal is transmitted through a serial interconnection to a first device using inputs that are also used by the first device to input other information thereto (e.g., data, commands, control signals). A generating circuit generates a device ID in response to the input signal. A transfer circuit then transfers an output signal associated with the device ID to a second device through a serial output of the first device. The serial output is also used by the first device to output other information (e.g., signals, data) to another device in the serial interconnection configuration.

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.

Abstract: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

Abstract: A non-volatile semiconductor memory device, comprising: an interface for receiving commands issued by a controller, the commands including an erase command; a functional entity with circuit components and having a terminal; a node; switchable circuitry capable of controllably switching between a first operational state in which the terminal is electrically connected to the node and a second operational state in which the terminal is electrically decoupled from the node, the node being configured to have a signal for the functional entity communicated through it when the switchable circuitry is in the first operational state; and a command processing unit configured to recognize the commands issued by the controller and, in response to recognizing the erase command, to cause the switchable circuitry to switch from the first operational state to the second operational state.

Abstract: Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.

Abstract: A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. The input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Adjusting the pre-charge voltage can result in power savings. When in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes.