Patents by Inventor Hamza Yilmaz

Hamza Yilmaz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055484
    Abstract: A field stop insulated gate bipolar transistor (IGBT) fabricated without back-side laser dopant activation or any process temperatures over 450° C. after fabrication of front-side IGBT structures provides activated injection regions with controlled dopant concentrations. Injection regions may be formed on or in a substrate by epitaxial growth or ion implants and diffusion before growth of N field stop and drift layers and front-side fabrication of IGBT active cells. Back-side material removal can expose the injection region(s) for electrical connection to back-side metal. Alternatively, after front-side fabrication of IGBT active cells, back-side material removal can expose the field stop layer (or injection regions) and sputtering using a silicon target with a well-controlled doping concentration can form hole or electron injection regions with well-controlled doping concentration.
    Type: Application
    Filed: October 12, 2023
    Publication date: February 15, 2024
    Inventor: Hamza Yilmaz
  • Patent number: 11824090
    Abstract: A field stop insulated gate bipolar transistor (IGBT) fabricated without back-side laser dopant activation or any process temperatures over 450° C. after fabrication of front-side IGBT structures provides activated injection regions with controlled dopant concentrations. Injection regions may be formed on or in a substrate by epitaxial growth or ion implants and diffusion before growth of N field stop and drift layers and front-side fabrication of IGBT active cells. Back-side material removal can expose the injection region(s) for electrical connection to back-side metal. Alternatively, after front-side fabrication of IGBT active cells, back-side material removal can expose the field stop layer (or injection regions) and sputtering using a silicon target with a well-controlled doping concentration can form hole or electron injection regions with well-controlled doping concentration.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: November 21, 2023
    Inventor: Hamza Yilmaz
  • Patent number: 11640992
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: May 2, 2023
    Assignees: IPOWER SEMICONDUCTOR, TAIWAN SEMICONDUCTOR CO., LTD.
    Inventors: Hamza Yilmaz, Jong Oh Kim
  • Patent number: 11640993
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: May 2, 2023
    Assignees: IPOWER SEMICONDUCTOR, TAIWAN SEMICONDUCTOR CO., LTD.
    Inventors: Hamza Yilmaz, Jong Oh Kim
  • Patent number: 11640994
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: May 2, 2023
    Assignees: IPOWER SEMICONDUCTOR, TAIWAN SEMICONDUCTOR CO., LTD.
    Inventors: Hamza Yilmaz, Jong Oh Kim
  • Publication number: 20230104778
    Abstract: A high voltage edge termination structure for a power semiconductor device is provided. The high voltage edge termination structure comprises a semiconductor body of a first conductive type, a JTE region of a second conductive type, a heavily doped channel stop region of the first conductive type, and a plurality of field plates. The JTE region is formed in the semiconductor body, wherein the JTE region is adjacent to an active region of the power semiconductor device. The heavily doped channel stop region is formed in the semiconductor body, wherein the heavily doped channel stop region is spaced apart from the JTE region. The plurality of field plates is formed on the JTE region.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 6, 2023
    Inventors: HAMZA YILMAZ, ARYADEEP MRINAL
  • Publication number: 20230108668
    Abstract: A high voltage edge termination structure for a power semiconductor device is provided. The high voltage edge termination structure comprises a semiconductor body of a first conductive type, a JTE region of a second conductive type, a heavily doped channel stop region of the first conductive type, and a plurality of field plates. The JTE region is formed in the semiconductor body, wherein the JTE region is adjacent to an active region of the power semiconductor device. The heavily doped channel stop region is formed in the semiconductor body, wherein the heavily doped channel stop region is spaced apart from the JTE region. The plurality of field plates is formed on the JTE region.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 6, 2023
    Inventors: HAMZA YILMAZ, ARYADEEP MRINAL
  • Publication number: 20230103304
    Abstract: A high voltage edge termination structure for a power semiconductor device is provided. The high voltage edge termination structure comprises a semiconductor body of a first conductive type, a JTE region of a second conductive type, a heavily doped channel stop region of the first conductive type, and a plurality of field plates. The JTE region is formed in the semiconductor body, wherein the JTE region is adjacent to an active region of the power semiconductor device. The heavily doped channel stop region is formed in the semiconductor body, wherein the heavily doped channel stop region is spaced apart from the JTE region. The plurality of field plates is formed on the JTE region.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 6, 2023
    Inventors: HAMZA YILMAZ, ARYADEEP MRINAL
  • Publication number: 20230100800
    Abstract: A shield trench power device such as a trench MOSFET or IGBT includes a substrate or an epitaxial layer of silicon, silicon carbide, gallium nitride, or gallium arsenide and employs an in-trench structure including a gate structure and an underlying polysilicon or oxide shield region that contacts a shield region in an epitaxial or crystalline layer of the device. The poly silicon region may be laterally confined by spacers in a gate trench and may contact or be isolated from the underlying shield region. Alternatively, the polysilicon region may be replaced with an insulating region.
    Type: Application
    Filed: December 1, 2022
    Publication date: March 30, 2023
    Inventor: Hamza Yilmaz
  • Patent number: 11594613
    Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.
    Type: Grant
    Filed: June 13, 2021
    Date of Patent: February 28, 2023
    Assignee: Alpha and Omega Semiconductor, Ltd.
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
  • Patent number: 11581432
    Abstract: The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: February 14, 2023
    Assignee: IPOWER SEMICONDUCTOR
    Inventor: Hamza Yilmaz
  • Patent number: 11538911
    Abstract: A shield trench power device such as a trench MOSFET or IGBT employs a gate structure with an underlying polysilicon shield region overlying a shield region in an epitaxial or crystalline layer of the device. The polysilicon region may be laterally confined by spacers in a gate trench and may contact or be isolated from the underlying shield region. Alternatively, the polysilicon region may be replaced with an insulating region.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: December 27, 2022
    Assignee: iPower Semiconductor
    Inventor: Hamza Yilmaz
  • Patent number: 11469313
    Abstract: A self-aligned p+ contact MOSFET device is provided. A process to manufacture the device includes forming oxide plugs on top of gate trenches, conducting uniform silicon mesa etch back, and forming oxide spacers to form contact trenches.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: October 11, 2022
    Assignee: IPOWER SEMICONDUCTOR
    Inventors: Hamza Yilmaz, Jong Oh Kim
  • Patent number: 11371721
    Abstract: A thermostatic radiator valve (TRV) assembly or automatic temperature balanced actuator (ABA) assembly controls a manifold assembly through a push pin bearing mechanism. The push pin bearing mechanism comprises a push pin that moves in a linear direction responsive to rotational movement of a motor gear that is coupled through a helical gear. Rotational movement of the push pin is prevented by a ball bearing assembly. Movement of the push pin is transferred to a manifold pin, which in turn, controls the manifold assembly. Because the push pin moves in a linear rather than a rotational fashion, erosion of the mated manifold pin is substantially reduced with respect to transitional approaches.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: June 28, 2022
    Assignee: Computime Ltd.
    Inventors: Dick Kwai Chan, Hamza Yilmaz, Ben Ren Tan, Wai-Leung Ha
  • Publication number: 20220157951
    Abstract: A high voltage edge termination structure for a power semiconductor device is provided. The high voltage edge termination structure comprises a semiconductor body of a first conductive type, a JTE region of a second conductive type, a heavily doped channel stop region of the first conductive type, and a plurality of field plates. The JTE region is formed in the semiconductor body, wherein the JTE region is adjacent to an active region of the power semiconductor device. The heavily doped channel stop region is formed in the semiconductor body, wherein the heavily doped channel stop region is spaced apart from the JTE region. The plurality of field plates is formed on the JTE region.
    Type: Application
    Filed: November 17, 2020
    Publication date: May 19, 2022
    Inventors: Hamza YILMAZ, Aryadeep MRINAL
  • Publication number: 20220131001
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Application
    Filed: January 11, 2022
    Publication date: April 28, 2022
    Applicants: IPOWER SEMICONDUCTOR, Taiwan Semiconductor Co., Ltd.
    Inventors: HAMZA YILMAZ, JONG OH KIM
  • Publication number: 20220131000
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Application
    Filed: January 11, 2022
    Publication date: April 28, 2022
    Applicants: IPOWER SEMICONDUCTOR, Taiwan Semiconductor Co., Ltd.
    Inventors: HAMZA YILMAZ, JONG OH KIM
  • Publication number: 20220130999
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Application
    Filed: January 11, 2022
    Publication date: April 28, 2022
    Applicants: IPOWER SEMICONDUCTOR, Taiwan Semiconductor Co., Ltd.
    Inventors: HAMZA YILMAZ, JONG OH KIM
  • Patent number: 11251297
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: February 15, 2022
    Assignees: Ipower Semiconductor, Taiwan Semiconductor Co., Ltd.
    Inventors: Hamza Yilmaz, Jong Oh Kim
  • Patent number: 11239352
    Abstract: A vertical IGBT device is disclosed. The vertical IGBT structure includes an active MOSFET cell array formed in an active region at a front side of a semiconductor substrate of a first conductivity type. One or more column structures of a second conductivity type concentrically surround the active MOSFET cell array. Each column structure includes a column trench and a deep column region. The deep column region is formed by implanting implants of the second conductivity type into the semiconductor substrate through the floor of the column trench. Dielectric side wall spacers are formed on the trench side walls except a bottom wall of the trench and the column trench is filled with poly silicon of the second conductivity type. One or more column structures are substantially deeper than the active MOSFET cell array.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: February 1, 2022
    Assignee: IPOWER SEMICONDUCTOR
    Inventor: Hamza Yilmaz