Patents by Inventor Hamza Yilmaz

Hamza Yilmaz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210057557
    Abstract: A vertical IGBT device is provided. The vertical IGBT device includes a substrate having a first conductivity type. A drift region of the first conductivity type formed on the top surface of the substrate. The bottom surface of the substrate is patterned to have an array of mesas and grooves. The mesas and the grooves are formed in an alternating fashion so that each mesa is separated from the other by a groove including a groove surface. In the groove surface, a top buffer region of the first conductivity type and a bottom buried region of a second conductivity type are formed extending laterally between the mesas adjacent each groove surface. Each mesa includes an upper region of the first conductivity and a lower region of the second conductivity.
    Type: Application
    Filed: November 8, 2020
    Publication date: February 25, 2021
    Applicant: IPOWER SEMICONDUCTOR
    Inventor: HAMZA YILMAZ
  • Publication number: 20210057556
    Abstract: A vertical IGBT device is provided. The vertical IGBT device includes a substrate having a first conductivity type. A drift region of the first conductivity type formed on the top surface of the substrate. The bottom surface of the substrate is patterned to have an array of mesas and grooves. The mesas and the grooves are formed in an alternating fashion so that each mesa is separated from the other by a groove including a groove surface. In the groove surface, a top buffer region of the first conductivity type and a bottom buried region of a second conductivity type are formed extending laterally between the mesas adjacent each groove surface. Each mesa includes an upper region of the first conductivity and a lower region of the second conductivity.
    Type: Application
    Filed: November 7, 2020
    Publication date: February 25, 2021
    Applicant: IPOWER SEMICONDUCTOR
    Inventor: HAMZA YILMAZ
  • Publication number: 20210055006
    Abstract: A thermostatic radiator valve (TRV) assembly or automatic temperature balanced actuator (ABA) assembly controls a manifold assembly through a push pin bearing mechanism. The push pin bearing mechanism comprises a push pin that moves in a linear direction responsive to rotational movement of a motor gear that is coupled through a helical gear. Rotational movement of the push pin is prevented by a ball bearing assembly. Movement of the push pin is transferred to a manifold pin, which in turn, controls the manifold assembly. Because the push pin moves in a linear rather than a rotational fashion, erosion of the mated manifold pin is substantially reduced with respect to transitional approaches.
    Type: Application
    Filed: November 9, 2020
    Publication date: February 25, 2021
    Inventors: Dick Kwai Chan, Hamza Yilmaz, Ben Ren Tan, Wai-Leung Ha
  • Publication number: 20210020567
    Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Inventors: Jun Hu, Madhur Bobde, Hamza Yilmaz
  • Patent number: 10897374
    Abstract: Building blocks for a smart device such as a thermostat include a user interface (UI) unit and a terminal (TML) unit. A UI unit may support one or more input data from a user and/or sensors and/or one or more control terminals. The UI unit may process each input datum or a combination of the input data, generate a control signal to one or more control terminals based on the processing, and send the control signal to one or more control terminals over a communication channel. A terminal unit, which may consist of one or more control terminals, transforms the received control signal into one or more controls to one or more associated environmental generators. One or more UI units may control one or more controlled apparatuses in conjunction with a mobile app to allow a unified user experience.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: January 19, 2021
    Assignee: Computime Ltd.
    Inventors: Hung Bun Choi, Wai-Leung Ha, Leung Yin Chan, Yau Wai Ng, Chi Chung Liu, Luke Li, Tsz Kin Lee, Chi Lung Chan, Hamza Yilmaz
  • Patent number: 10871293
    Abstract: A thermostatic radiator valve (TRV) assembly or automatic temperature balanced actuator (ABA) assembly controls a manifold assembly through a push pin bearing mechanism. The push pin bearing mechanism comprises a push pin that moves in a linear direction responsive to rotational movement of a motor gear that is coupled through a helical gear. Rotational movement of the push pin is prevented by a ball bearing assembly. Movement of the push pin is transferred to a manifold pin, which in turn, controls the manifold assembly. Because the push pin moves in a linear rather than a rotational fashion, erosion of the mated manifold pin is substantially reduced with respect to transitional approaches.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 22, 2020
    Assignee: Computime Ltd.
    Inventors: Dick Kwai Chan, Hamza Yilmaz, Ben Ren Tan, Wai-Leung Ha
  • Patent number: 10804355
    Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.
    Type: Grant
    Filed: January 27, 2019
    Date of Patent: October 13, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Jun Hu, Madhur Bobde, Hamza Yilmaz
  • Publication number: 20200303513
    Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.
    Type: Application
    Filed: May 31, 2020
    Publication date: September 24, 2020
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
  • Publication number: 20200303507
    Abstract: A shield trench power device such as a trench MOSFET or IGBT employs a gate structure with an underlying polysilicon shield region overlying a shield region in an epitaxial or crystalline layer of the device. The polysilicon region may be laterally confined by spacers in a gate trench and may contact or be isolated from the underlying shield region. Alternatively, the polysilicon region may be replaced with an insulating region.
    Type: Application
    Filed: June 4, 2020
    Publication date: September 24, 2020
    Inventor: Hamza Yilmaz
  • Patent number: 10777661
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly silicon oxide (IPO) layer. The IPO layer can be formed by either depositing a silicon oxide layer or thermally growing a poly silicon oxide layer with minimal thickness variation. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 15, 2020
    Assignee: IPOWER SEMICONDUCTOR
    Inventor: Hamza Yilmaz
  • Publication number: 20200279926
    Abstract: Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.
    Type: Application
    Filed: December 5, 2019
    Publication date: September 3, 2020
    Applicant: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Hamza Yilmaz, Richard A. Blanchard
  • Patent number: 10755931
    Abstract: A semiconductor device includes a superjunction structure formed using simultaneous N and P angled implants into the sidewall of a trench. The simultaneous N and P angled implants use different implant energies and dopants of different diffusion rate so that after annealing, alternating N and P thin semiconductor regions are formed. The alternating N and P thin semiconductor regions form a superjunction structure where a balanced space charge region is formed to enhance the breakdown voltage characteristic of the semiconductor device.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: August 25, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Karthik Padmanabhan, Madhur Bobde, Lingpeng Guan, Lei Zhang, Hamza Yilmaz
  • Patent number: 10714574
    Abstract: A shield trench power device such as a trench MOSFET or IGBT employs a gate structure with an underlying polysilicon shield region that contacts a shield region in an epitaxial or crystalline layer of the device.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: July 14, 2020
    Assignee: iPower Semiconductor
    Inventor: Hamza Yilmaz
  • Publication number: 20200203514
    Abstract: A vertical IGBT device is disclosed. The vertical IGBT structure includes an active MOSFET cell array formed in an active region at a front side of a semiconductor substrate of a first conductivity type. One or more column structures of a second conductivity type concentrically surround the active MOSFET cell array. Each column structure includes a column trench and a deep column region. The deep column region is formed by implanting implants of the second conductivity type into the semiconductor substrate through the floor of the column trench. Dielectric side wall spacers are formed on the trench side walls except a bottom wall of the trench and the column trench is filled with poly silicon of the second conductivity type. One or more column structures are substantially deeper than the active MOSFET cell array.
    Type: Application
    Filed: February 28, 2020
    Publication date: June 25, 2020
    Applicant: IPOWER SEMICONDUCTOR
    Inventor: HAMZA YILMAZ
  • Patent number: 10686035
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: June 16, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Daniel Ng, Lingping Guan, Anup Bhalla, Wilson Ma, Moses Ho, John Chen
  • Patent number: 10680097
    Abstract: A semiconductor device, comprising: a substrate; an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; a gate pickup trench in the substrate; a first conductive region and a second conductive region disposed in the gate pickup trench, the first conductive region and the second conductive region being separated by oxide, wherein at least a portion of the oxide surrounding the first conductive region in the gate pickup trench is thicker than at least a portion of the oxide under the second conductive region; and a body region in the substrate.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: June 9, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: John Chen, Il Kwan Lee, Hong Chang, Wenjun Li, Anup Bhalla, Hamza Yilmaz
  • Publication number: 20200105874
    Abstract: A field stop insulated gate bipolar transistor (IGBT) fabricated without back-side laser dopant activation or any process temperatures over 450° C. after fabrication of front-side IGBT structures provides activated injection regions with controlled dopant concentrations. Injection regions may be formed on or in a substrate by epitaxial growth or ion implants and diffusion before growth of N field stop and drift layers and front-side fabrication of IGBT active cells. Back-side material removal can expose the injection region(s) for electrical connection to back-side metal. Alternatively, after front-side fabrication of IGBT active cells, back-side material removal can expose the field stop layer (or injection regions) and sputtering using a silicon target with a well-controlled doping concentration can form hole or electron injection regions with well-controlled doping concentration.
    Type: Application
    Filed: June 13, 2019
    Publication date: April 2, 2020
    Inventor: Hamza Yilmaz
  • Publication number: 20200105866
    Abstract: Semiconductor devices and methods of fabrication are provided. The semiconductor device includes a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD) to control charge injection by lowering carrier storage. The device can have a first conductivity type semiconductor substrate, and a drift region that includes a doped buffer region, a doped middle region and a doped field stop region or carrier storage region. The device can also include a second conductivity type shield region comprising a deep junction encircling (or substantially laterally beneath) the buffer region and a second conductivity type shallow junction anode region in electrical contact with a second conductivity type anode electrode. The deep junction can have a range of doping concentrations surrounding the buffer regions to deplete buffer charge laterally as well as vertically to prevent premature device breakdown. The first conductivity type may be N type and the second conductivity type may be P type.
    Type: Application
    Filed: June 24, 2019
    Publication date: April 2, 2020
    Inventor: Hamza Yilmaz
  • Patent number: 10608092
    Abstract: This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.
    Type: Grant
    Filed: December 16, 2017
    Date of Patent: March 31, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, John Chen, Daniel Ng, Wenjun Li
  • Patent number: 10593759
    Abstract: Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer. The thicknesses and doping concentrations of the first and second epitaxial layers and the mesa are selected to achieve charge balance in operation. In another embodiment, the semiconductor body is lightly doped and the thicknesses and doping concentrations of the first and second epitaxial layers are selected to achieve charge balance in operation.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: March 17, 2020
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang