Patents by Inventor Han Chang

Han Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190244957
    Abstract: A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source/drain structure, a conductor, and a contact etch stop layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure, in which the first spacer has a top portion and a bottom portion between the top portion and the substrate. The source/drain structure is present adjacent to the bottom portion of the first spacer. The conductor is electrically connected to the source/drain structure. The protection layer is present at least between the conductor and the top portion of the first spacer. The contact etch stop layer is present at least partially between the conductor and the bottom portion of the first spacer while absent between the protection layer and the top portion of the first spacer.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Publication number: 20190244864
    Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Shahaji B. More, Zheng-Yang Pan, Cheng-Han Lee, Shih-Chieh Chang
  • Publication number: 20190244863
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10374003
    Abstract: A semiconductor light emitting device includes a plurality of light emitting cells having first and second surface opposing each other, the plurality of light emitting cells including a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer therebetween, an insulating layer on the second surface of the plurality of light emitting cells and having first and second openings defining a first contact region of the first conductivity-type semiconductor layer and a second contact region of the second conductivity-type semiconductor layer, respectively, a connection electrode on the insulating layer and connecting a first contact region and a second contact region of adjacent light emitting cells, a transparent support substrate on the first surface of the plurality of light emitting cells, and a transparent bonding layer between the plurality of light emitting cells and the transparent support substrate.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pun Jae Choi, Jacob Chang-Lin Tarn, Han Kyu Seong, Jin Hyuk Song, Yoon Joon Choi
  • Patent number: 10366990
    Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10366915
    Abstract: A semiconductor device includes a first gate structure disposed over a substrate. The first gate structure extends in a first direction. A second gate structure is disposed over the substrate. The second gate structure extends in the first direction. A dielectric material is disposed between the first gate structure and the second gate structure. An air gap is disposed within the dielectric material.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10365561
    Abstract: Shrinkage and mass losses are reduced in photoresist exposure and post exposure baking by utilizing a small group which will decompose. Alternatively a bulky group which will not decompose or a combination of the small group which will decompose along with the bulky group which will not decompose can be utilized. Additionally, polar functional groups may be utilized in order to reduce the diffusion of reactants through the photoresist.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Han Lai, Ching-Yu Chang, Chen-Hau Wu
  • Patent number: 10367079
    Abstract: A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation structure and engaging the fin; and a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack. The semiconductor device further includes a first dielectric layer vertically between the fin and the gate spacer and in physical contact with the sidewall of the gate stack, wherein the first dielectric layer has a laterally extending cavity. The semiconductor device further includes a second dielectric layer filling in the cavity, wherein the first and second dielectric layers include different materials.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Jr-Jung Lin, Shih-Hao Chen, Chih-Han Lin, Mu-Tsang Lin, Yung Jung Chang
  • Patent number: 10366966
    Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer and a core material layer are sequentially formed on a first carrier. A portion of the core material layer is removed to form a core layer having a plurality of cavities. The first carrier, the dielectric layer, and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. The first carrier is removed from the dielectric layer. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo
  • Patent number: 10366926
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Publication number: 20190223776
    Abstract: A urinary bladder irrigation device includes: a first pipe, a second pipe, a third pipe, a liquid supply member, a liquid collection member, a detection member, and an elevation member. The first pipe has a first opening at one end thereof. The second pipe has a second opening at one end thereof. The third pipe has an end connected to another end of the first pipe and another end of the second pipe and has a third opening at another end thereof. The liquid supply member is connected to the first opening. The liquid collection member is connected to the second opening. The detection member is positioned in the second pipe. The elevation member accommodates the detection member.
    Type: Application
    Filed: January 24, 2019
    Publication date: July 25, 2019
    Inventors: Chen-Hsun Weng, Ming-Chien Hung, Wen-Horng Yang, Chien-Hui Ou, Ming-Huang Chen, Chih-Han Chang
  • Publication number: 20190229215
    Abstract: A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10355110
    Abstract: A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Po-Chi Wu, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10352698
    Abstract: Disclosed is a composite hydrological monitoring system, in which a counterweight component and a test component are respectively connected to both opposite ends of a strip and a plurality of sensors are disposed at different vertical positions. Accordingly, the scour depth can be measured by sensing the location of the counterweight component, whereas the water level and/or flow velocity can be determined by signals from the sensors. When the counterweight component moves downward with sinking of the riverbed, the strip would be pulled down and thus causes the test component to present a change in mechanical energy. Accordingly, the sinking depth can be measured by sensing the change of the mechanical energy. Additionally, since the water level variation would cause signal changes of the sensors arranged in a row along a vertical direction, the change of water level can be determined accordingly.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: July 16, 2019
    Assignee: National Applied Research Laboratories
    Inventors: Yung-Bin Lin, Yu-Chieh Chen, Tai-Shan Liao, Kuo-Chun Chang, Bo-Han Lee, Yung-Kang Wang, Meng-Huang Gu
  • Patent number: 10347764
    Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 10349160
    Abstract: A headset controller takes a first touch sensor, a second touch sensor, a first pressure sensor, and a second pressure sensor as a control medium for users. The headset controller can generate four different output instructions by the users touching or pressing the operating interface. The headset controller integrates various sensing methods to generate the needed output instructions.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: July 9, 2019
    Assignee: PIXART IMAGING INC.
    Inventors: Jung-Tai Lin, En-Feng Hsu, Han-Chang Lin
  • Publication number: 20190204259
    Abstract: A method includes steps of: applying a first voltage signal on a blood sample so as to obtain a preliminary value regarding an analyte in the blood sample; applying on the blood sample, a second voltage signal that includes cycles of a pulse and that has a voltage value alternating between high and low levels; measuring a physical quantity resulting from application of the second voltage signal on the blood sample at a time point in one of the cycles of the pulse of the second voltage signal so as to generate a calibration value; and calibrating the preliminary value based on the calibration value so as to obtain a calibrated value of the analyte in the blood sample which serves as a result of measurement of the analyte.
    Type: Application
    Filed: November 21, 2018
    Publication date: July 4, 2019
    Inventors: Meng-Yi LIN, Po-Han CHEN, Pei-Chen CHANG
  • Publication number: 20190201599
    Abstract: The present invention relates to a negative pressure wound therapy device, system and method. The negative pressure wound therapy device is connected with a dressing, and comprises a housing, a control circuit board, a pump, and an aspiration conduit. The pump generates negative pressure. The pump may comprise a voltage-actuated deformation element (such as piezoelectric vibration element) to push fluid from an aspiration end to a discharge end. The aspiration conduit has a pump end and a dressing end. The pump end is fluidly connected to the aspiration end of the pump, and the dressing end is fluidly connected to the dressing used for covering a wound. The control circuit board is disposed in the housing, controls the pump to generate the negative pressure in the aspiration conduit, and applies negative pressure to the wound covered by the dressing via the aspiration conduit.
    Type: Application
    Filed: December 6, 2018
    Publication date: July 4, 2019
    Inventors: PO-HAN CHANG, SHIH HUA HSIAO, BO CHENG HUANG, CHI YUAN CHEN, TING HSUAN CHUNG
  • Publication number: 20190206680
    Abstract: Provided is a material composition and method for substrate modification. A substrate is patterned to include a plurality of features. The plurality of features includes a first subset of features having one or more substantially inert surfaces. In various embodiments, a priming material is deposited over the substrate, over the plurality of features, and over the one or more substantially inert surfaces. By way of example, the deposited priming material bonds at least to the one or more substantially inert surfaces. Additionally, the deposited priming material provides a modified substrate surface. After depositing the priming material, a layer is spin-coated over the modified substrate surface, where the spin-coated layer is substantially planar.
    Type: Application
    Filed: December 20, 2018
    Publication date: July 4, 2019
    Inventors: Wei-Han LAI, Chien-Wei WANG, Ching-Yu CHANG, Chin-Hsiang LIN
  • Publication number: 20190204380
    Abstract: An embodiment includes a first lead guide, a second lead guide, and a handler. The first lead guide includes a first insulating housing and a first conductive contact having a face and a recessed face. The second lead guide includes a second insulating housing and a second conductive contact. The first and second lead guides are fastened to the handler.
    Type: Application
    Filed: January 24, 2018
    Publication date: July 4, 2019
    Inventors: Chi-Tsung LEE, Ching-Han CHANG, Chun-Hsien LU