Patents by Inventor Han-Hsin Kuo
Han-Hsin Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10062645Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.Type: GrantFiled: June 12, 2017Date of Patent: August 28, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Hsin Kuo, Chung-Chi Ko, Neng-Jye Yang, Fu-Ming Huang, Chi-Ming Tsai, Liang-Guang Chen
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Publication number: 20170278785Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.Type: ApplicationFiled: June 12, 2017Publication date: September 28, 2017Inventors: Han-Hsin Kuo, Chung-Chi Ko, Neng-Jye Yang, Fu-Ming Huang, Chi-Ming Tsai, Liang-Guang Chen
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Patent number: 9723915Abstract: A method for cleaning a brush includes inducing a static charge on a surface of a first plate, wherein the first plate comprises at least one of silicon nitride (SixNy) or silicon oxide (SiaOb), wherein a, b, x and y are integers. The method further includes rotating the brush in contact with the surface of the first plate.Type: GrantFiled: August 4, 2015Date of Patent: August 8, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Ming Huang, Liang-Guang Chen, Han-Hsin Kuo, Chi-Ming Tsai, He Hui Peng
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Patent number: 9679848Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.Type: GrantFiled: September 30, 2016Date of Patent: June 13, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Hsin Kuo, Chung-Chi Ko, Neng-Jye Yang, Fu-Ming Huang, Chi-Ming Tsai, Liang-Guang Chen
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Patent number: 9630295Abstract: Embodiments of mechanisms for performing a chemical mechanical polishing (CMP) process are provided. A method for performing a CMP process includes polishing a wafer by using a polishing pad. The method also includes applying a cleaning liquid jet on the polishing pad to condition the polishing pad. A CMP system is also provided.Type: GrantFiled: July 17, 2013Date of Patent: April 25, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: He-Hui Peng, Fu-Ming Huang, Shich-Chang Suen, Han-Hsin Kuo, Chi-Ming Tsai, Liang-Guang Chen
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Publication number: 20170018496Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.Type: ApplicationFiled: September 30, 2016Publication date: January 19, 2017Inventors: Han-Hsin Kuo, Chung-Chi Ko, Neng-Jye Yang, Fu-Ming Huang, Chi-Ming Tsai, Liang-Guang Chen
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Patent number: 9460997Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.Type: GrantFiled: December 31, 2013Date of Patent: October 4, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Hsin Kuo, Chung-Chi Ko, Neng-Jye Yang, Fu-Ming Huang, Chi-Ming Tsai, Liang-Guang Chen
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Patent number: 9370854Abstract: The present disclosure provides a method of fabricating a semiconductor device with metal interconnections and a design of a tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device, the method includes providing a semiconductor substrate, depositing a dielectric layer over the semiconductor substrate, forming at least one trench in the dielectric layer, and forming a metallization layer in the trench and over the dielectric layer. The method further includes performing a chemical mechanical polishing process to planarize the metallization layer and the dielectric layer, performing a surface treatment on the planarized dielectric layer to form a protection layer, cleaning the planarized metallization layer and the treated dielectric layer to remove residue from the chemical mechanical polishing process, and drying the cleaned metallization layer and dielectric layer in an inert gas environment.Type: GrantFiled: November 13, 2013Date of Patent: June 21, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Hsin Kuo, Fu-Ming Huang
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Patent number: 9368452Abstract: The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.Type: GrantFiled: February 18, 2014Date of Patent: June 14, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Soon-Kang Huang, Han-Hsin Kuo, Chi-Ming Yang, Shwang-Ming Jeng, Chin-Hsiang Lin
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Patent number: 9305880Abstract: A semiconductor substructure with improved performance and a method of forming the same is described. The method includes providing a semiconductor dielectric layer having a recess formed therein; forming an interconnect structure with a metal liner and a conductive fill within the recess; and applying an electron beam treatment to the substructure.Type: GrantFiled: October 24, 2013Date of Patent: April 5, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Ming Huang, Han-Hsin Kuo, Chi-Ming Tsai, Liang-Guang Chen
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Patent number: 9252060Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches.Type: GrantFiled: April 1, 2012Date of Patent: February 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Tsai, Liang-Guang Chen, Han-Hsin Kuo, Fu-Ming Huang, Hao-Jen Liao, Ming-Chung Liang
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Publication number: 20150335146Abstract: A method for cleaning a brush includes inducing a static charge on a surface of a first plate, wherein the first plate comprises at least one of silicon nitride (SixNy) or silicon oxide (SiaOb), wherein a, b, x and y are integers. The method further includes rotating the brush in contact with the surface of the first plate.Type: ApplicationFiled: August 4, 2015Publication date: November 26, 2015Inventors: Fu-Ming HUANG, Liang-Guang CHEN, Han-Hsin KUO, Chi-Ming TSAI, He Hui PENG
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Patent number: 9119464Abstract: A brush cleaning system comprising: a plate comprising at least one of silicon nitride (SixNy) or silicon oxide (SiaOb), wherein the plate has a static charge on a surface thereof; and a machine configured to rotate a brush in contact with the static charged surface of the plate.Type: GrantFiled: January 31, 2012Date of Patent: September 1, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Ming Huang, Liang-Guang Chen, Han-Hsin Kuo, Chi-Ming Tsai, He Hui Peng
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Publication number: 20150187697Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.Type: ApplicationFiled: December 31, 2013Publication date: July 2, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Hsin Kuo, Chung-Chi Ko, Neng-Jye Yang, Fu-Ming Huang, Chi-Ming Tsai, Liang-Guang Chen
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Publication number: 20150132948Abstract: The present disclosure provides a method of fabricating a semiconductor device with metal interconnections and a design of a tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device, the method includes providing a semiconductor substrate, depositing a dielectric layer over the semiconductor substrate, forming at least one trench in the dielectric layer, and forming a metallization layer in the trench and over the dielectric layer. The method further includes performing a chemical mechanical polishing process to planarize the metallization layer and the dielectric layer, performing a surface treatment on the planarized dielectric layer to form a protection layer, cleaning the planarized metallization layer and the treated dielectric layer to remove residue from the chemical mechanical polishing process, and drying the cleaned metallization layer and dielectric layer in an inert gas environment.Type: ApplicationFiled: November 13, 2013Publication date: May 14, 2015Applicant: Taiwan Semiconductor Manufacturing CO., LTD.Inventors: Han-Hsin Kuo, Fu-Ming Huang
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Publication number: 20150115447Abstract: A semiconductor substructure with improved performance and a method of forming the same is described. The method includes providing a semiconductor dielectric layer having a recess formed therein; forming an interconnect structure with a metal liner and a conductive fill within the recess; and applying an electron beam treatment to the substructure.Type: ApplicationFiled: October 24, 2013Publication date: April 30, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Ming HUANG, Han-Hsin KUO, Chi-Ming TSAI, Liang-Guang CHEN
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Publication number: 20150087208Abstract: In a semiconductor wafer manufacturing apparatus, a rotation module is provided to hold the semiconductor wafer at a plane. The semiconductor wafer is revolved by the rotation module around a first axis. The first axis is substantially perpendicular to the plane. A cleaning module is configured to revolve around a second axis when the cleaning module contacts the surface of the semiconductor wafer. A mechanism is further provided to enable the rotation module and/or the cleaning module to move along a direction substantially perpendicular to the first axis. Consequently, the relative velocities at the contact points between the semiconductor wafer and the cleaning module are changed. Moreover, no relative velocity at any contact point between the semiconductor wafer and the cleaning module is zero or close to zero.Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: CHI-MING TSAI, HAN-HSIN KUO, FU-MING HUANG, LIANG-GUANG CHEN
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Publication number: 20150024661Abstract: Embodiments of mechanisms for performing a chemical mechanical polishing (CMP) process are provided. A method for performing a CMP process includes polishing a wafer by using a polishing pad. The method also includes applying a cleaning liquid jet on the polishing pad to condition the polishing pad. A CMP system is also provided.Type: ApplicationFiled: July 17, 2013Publication date: January 22, 2015Inventors: He-Hui PENG, Fu-Ming HUANG, Shich-Chang SUEN, Han-Hsin KUO, Chi-Ming TSAI, Liang-Guang CHEN
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Publication number: 20140159243Abstract: The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.Type: ApplicationFiled: February 18, 2014Publication date: June 12, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Soon-Kang Huang, Han-Hsin Kuo, Chi-Ming Yang, Shwang-Ming Jeng, Chin-Hsiang Lin
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Patent number: 8673783Abstract: The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.Type: GrantFiled: July 2, 2010Date of Patent: March 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huang Soon Kang, Han-Hsin Kuo, Chi-Ming Yang, Shwang-Ming Jeng, Chin-Hsiang Lin