Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die being bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.

Abstract: A method of forming a semiconductor memory device includes: forming a stack structure on a substrate, the stack structure including a plurality of dielectric layers and a plurality of sacrificial layers alternatingly stacked in a Z direction substantially perpendicular to the substrate; forming a plurality of source/drain trenches in the stack structure; conformally forming a barrier layer in the source/drain trenches, and then filling the source/drain trenches with a plurality of sacrificial segments; forming a protection layer over the stack structure to cover the barrier layer and the sacrificial segments; removing the sacrificial layers of the stack structure to form a plurality of spaces among the dielectric layers; forming a plurality of conductive layers in the spaces; sequentially removing the protection layer, the sacrificial segments and the barrier layer; and forming a plurality of memory structures in the source/drain trenches.

Abstract: A ferroelectric memory device includes a first conductive region, a second conductive region and a ferroelectric structure. The second conductive region is disposed over the first conductive region. The ferroelectric structure includes a plurality of different ferroelectric materials stacked between the first conductive region and the second conductive region.

Abstract: A semiconductor device includes a transistor and a ferroelectric tunnel junction. The ferroelectric tunnel junction is connected to a drain contact of the transistor. The ferroelectric tunnel junction includes a first electrode, a second electrode, a crystalline oxide layer, and a ferroelectric layer. The second electrode is disposed over the first electrode. The crystalline oxide layer and the ferroelectric layer are disposed in direct contact with each other in between the first electrode and the second electrode. The crystalline oxide layer comprises a crystalline oxide material. The ferroelectric layer comprises a ferroelectric material.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first dielectric layer over a substrate. A first conductive structure overlies the first dielectric layer. A data storage structure is disposed between the first dielectric layer and the first conductive structure. The data storage structure comprises a data storage layer and a grid structure. The grid structure comprises a plurality of opposing sidewalls spaced across a width of the first conductive structure. The data storage layer is disposed along the plurality of opposing sidewalls. The data storage layer comprises a first material and the grid structure comprises a second material different from the first material.

Abstract: In an embodiment, a device includes: a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer.

Abstract: An embodiment method of forming a first wafer, which is a component of a wafer-to-wafer bonded structure, may include forming a plurality of electronic circuits in a semiconductor material layer of a substrate of the first wafer, forming an interconnect layer including electrical interconnect structures over the plurality of electronic circuits such that the electrical interconnect structures are electrically connected to the plurality of electronic circuits, forming a first dielectric window structure that extends through the semiconductor material layer and into the substrate, and removing a back-side portion of the substrate to reveal the first dielectric window structure. The method may further include placing the first wafer in proximity to a second wafer, directing visible light through the first dielectric window structure, and observing or recording an image, generated by the visible light, of first alignment marks of the first wafer and second alignment marks of the second wafer.

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

Abstract: A 3D memory array has data storage structures provided at least in part by one or more vertical films that do not extend between vertically adjacent memory cells. The 3D memory array includes conductive strips and dielectric strips, alternately stacked over a substrate. The conductive strips may be laterally indented from the dielectric strips to form recesses. A data storage film may be disposed within these recesses. Any portion of the data storage film deposited outside the recesses may have been effectively removed, whereby the data storage film is essentially discontinuous from tier to tier within the 3D memory array. The data storage film within each tier may have upper and lower boundaries that are the same as those of a corresponding conductive strip. The data storage film may also be made discontinuous between horizontally adjacent memory cells.

Abstract: A semiconductor device includes a transistor and a ferroelectric tunnel junction. The ferroelectric tunnel junction is connected to a drain contact of the transistor. The ferroelectric tunnel junction includes a first electrode, a second electrode, a crystalline oxide layer, and a ferroelectric layer. The second electrode is disposed over the first electrode. The crystalline oxide layer and the ferroelectric layer are disposed in direct contact with each other in between the first electrode and the second electrode. The crystalline oxide layer comprises a crystalline oxide material. The ferroelectric layer comprises a ferroelectric material.

Abstract: A magnetic tunnel junction memory device includes a vertical stack of magnetic tunnel junction NOR strings located over a substrate. Each magnetic tunnel junction NOR string includes a respective semiconductor material layer that contains a semiconductor source region, a plurality of semiconductor channels, and a plurality of semiconductor drain regions, a plurality of magnetic tunnel junction memory cells having a respective first electrode that is located on a respective one of the plurality of semiconductor drain regions, and a metallic bit line contacting each second electrode of the plurality of magnetic tunnel junction memory cells. The vertical stack of magnetic tunnel junction NOR strings may be repeated along a channel direction to provide a three-dimensional magnetic tunnel junction memory device.

Abstract: A memory device includes a substrate, a first stacking structure, a second stacking structure, struts, an isolation structure, memory films, channel layers, and conductive pillars. The first stacking structure includes first gate layers and is located on the substrate. The second stacking structure includes second gate layers and is located on the substrate, where the second stacking structure is separated from the first stacking structure through a trench. The struts stand on the substrate and are located in the trench, where the struts each have two opposite surfaces respectively in contact with the first stacking structure and the second stacking structure. The isolation structure stands on the substrate and is located in the trench, where cell regions are located in the trenches, and at least two of the cell regions are separated from one another through a respective one strut and the isolation structure connected therewith.

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

Abstract: Memories are provided. A memory includes a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array, a plurality of static random access memory (SRAM) cells arranged in a second memory array, and a controller configured to access the first memory array and the second memory array with different access rate. Each of the FRAM cells includes a ferroelectric field-effect transistor (FeFET). A gate structure of the FeFET includes a gate electrode over a channel of the FeFET, a ferroelectric layer over the gate electrode, a first electrode over the gate electrode, and a second electrode over the first electrode. The ferroelectric layer is formed between the first and second electrodes.

Abstract: A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.

Abstract: A magnetoresistive stack, including an electrically conductive material, and a seed region disposed above the electrically conductive material and including chromium (Cr). A chromium content of the seed region is large enough to render the seed region substantially non-magnetic. The magnetoresistive stack includes a fixed magnetic region disposed above the seed region. The fixed magnetic region includes a synthetic antiferromagnetic structure including a first ferromagnetic region disposed above the seed region, a coupling layer disposed on and in contact with the first ferromagnetic region, and a second ferromagnetic region disposed on and in contact with the coupling layer. The magnetoresistive stack includes one or more dielectric layers disposed above the second ferromagnetic region, and a free magnetic region disposed above the one or more dielectric layers.

Abstract: A device includes stacking structures. Each of the stacking structures includes alternately stacked first conductive lines and first dielectric layers, and the first conductive lines has first sides and second sides opposite to the first sides. The device further includes a plurality of second conductive lines crossing over the first conductive lines. Widths of the second conductive lines are increased as the second conductive lines become far away from the first sides.

Abstract: A semiconductor chip including a semiconductor substrate, an interconnect structure and a memory cell array is provided. The semiconductor substrate includes a logic circuit. The interconnect structure is disposed on the semiconductor substrate and electrically connected to the logic circuit, and the interconnect structure includes stacked interlayer dielectric layers and interconnect wirings embedded in the stacked interlayer dielectric layers. The memory cell array is embedded in the stacked interlayer dielectric layers. The memory cell array includes driving transistors and memory devices, and the memory devices are electrically connected the driving transistors through the interconnect wirings.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking 10 structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.

Abstract: Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.