Patents by Inventor Hanan Potash

Hanan Potash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020114595
    Abstract: A system and method are presented for efficient installation of a data conduit in a previously fluid distribution pipe. In an embodiment, the data conduit may be an optical fiber within a communications network, and the fluid distribution pipe may be a water pipe within the plumbing system of a building. The method assumes no special features or provisions in the building construction, except a standard plumbing system, or similar network of fluid-conveying pipes. Compared to existing fiber installation methods, in which conduit must be placed within walls and ceiling throughout the building, the approach disclosed herein is believed to require less effort and to entail simpler modifications to the building. The use of existing pipes as conduits also enables a convenient technique for routing the optical fiber by using the flow of water to automatically direct a pull cable to the intended exit point.
    Type: Application
    Filed: February 16, 2001
    Publication date: August 22, 2002
    Inventor: Hanan Potash
  • Publication number: 20020103847
    Abstract: A method and system are presented for data communication between multiple concurrently-active threads, preferably executing on a multithreaded processor, such as a precession machine. Compared to existing methods for inter-thread communication, such as calls interrupts, the method described herein reduces overhead associated with context switching and avoids devoting the processor exclusively to the called thread while it executes. The method disclosed herein is therefore believed to offer higher performance for applications such as communications protocol processing, in which there may be a high level of concurrent activity among the threads.
    Type: Application
    Filed: February 1, 2001
    Publication date: August 1, 2002
    Inventor: Hanan Potash
  • Publication number: 20020103990
    Abstract: An architecture and method are presented for a computer processor supporting interleaved execution of multiple concurrently-active threads, and capable of independently allocating a portion of the total processor execution time to each of the threads. Compared to existing architectures, in which the portion of processor time allocated to each thread is fixed, the processor architecture described herein is believed to offer higher performance for applications such as communications protocol processing, in which the workload of individual threads may vary, and in which the workload requires real time facilities.
    Type: Application
    Filed: February 1, 2001
    Publication date: August 1, 2002
    Inventor: Hanan Potash
  • Patent number: 6340588
    Abstract: Combinations, called matrices with memories, of matrix materials that are encoded with an optically readable code are provided. The matrix materials are those that are used in as supports in solid phase chemical and biochemical syntheses, immunoassays and hybridization reactions. The matrix materials may additionally include fluophors or other luminescent moieties to produce luminescing matrices with memories. The memories include electronic and optical storage media and also include optical memories, such as bar codes and other machine-readable codes. By virtue of this combination, molecules and biological particles, such as phage and viral particles and cells, that are in proximity or in physical contact with the matrix combination can be labeled by programming the memory with identifying information and can be identified by retrieving the stored information. Combinations of matrix materials, memories, and linked molecules and biological materials are also provided.
    Type: Grant
    Filed: September 22, 1998
    Date of Patent: January 22, 2002
    Assignee: Discovery Partners International, Inc.
    Inventors: Michael P. Nova, Hanan Potash
  • Patent number: 6329139
    Abstract: Automated drug discovery protocols, or partially automated protocols, in which matrices with memories serve as the platform on which all manipulations are performed or serve as the repository of information that is transferred to other memories as the synthesized compounds are processed and screened. Also provided are automated drug discovery units for use in the protocols. The units provide a means for seamless data tracking and include instrumentation and vials with memories for information transfer to other memories in a unit. The units, which are provided herein, include some or all of the following: an automated or manual sorter, microvessels, which contain memories, an automated or semi-automated synthesizer, a microvessel washer/dryer, a manual or automated cleaver for removing compounds from the matrix with memory microvessels, and associated software. The memories may be any of any type, including electromagnetically encodable memories and optical memories, or combinations thereof.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: December 11, 2001
    Assignee: Discovery Partners International
    Inventors: Michael P. Nova, John E. Lillig, Kanchana Sanjaya Gunesekera Karunaratne, William Ewing, Yozo Satoda, Hanan Potash
  • Patent number: 6319668
    Abstract: Combinations, called matrices with memories, of matrix materials that are encoded with an optically readable code are provided. The matrix materials are those that are used in as supports in solid phase chemical and biochemical syntheses, immunoassays and hybridization reactions. The matrix materials may additionally include fluophors or other luminescent moieties to produce luminescing matrices with memories. The memories include electronic and optical storage media and also include optical memories, such as bar codes and other machine-readable codes. By virtue of this combination, molecules and biological particles, such as phage and viral particles and cells, that are in proximity or in physical contact with the matrix combination can be labeled by programming the memory with identifying information and can be identified by retrieving the stored information. Combinations of matrix materials, memories, and linked molecules and biological materials are also provided.
    Type: Grant
    Filed: June 24, 1996
    Date of Patent: November 20, 2001
    Assignee: Discovery Partners International
    Inventors: Michael P. Nova, Hanan Potash, Xiao-Yi Xiao, Zahra Parandoosh, Gary S. David
  • Patent number: 6284459
    Abstract: Combinations, called matrices with memories, of matrix materials that are encoded with an optically readable code are provided. The matrix materials are those that are used in as supports in solid phase chemical and biochemical syntheses, immunoassays and hybridization reactions. The matrix materials may additionally include fluophors or other luminescent moieties to produce luminescing matrices with memories. The memories include electronic and optical storage media and also include optical memories, such as bar codes and other machine-readable codes. By virtue of this combination, molecules and biological particles, such as phage and viral particles and cells, that are in proximity or in physical contact with the matrix combination can be labeled by programming the memory with identifying information and can be identified by retrieving the stored information. Combinations of matrix materials, memories, and linked molecules and biological materials are also provided.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: September 4, 2001
    Assignee: Discovery Partners International
    Inventors: Michael P. Nova, Andrew E. Senyei, Xiao-Yi Xiao, Chanfeng Zhao, Hanan Potash
  • Patent number: 6100026
    Abstract: Combinations, called matrices with memories, of matrix materials that are encoded with an optically readable code are provided. The matrix materials are those that are used in as supports in solid phase chemical and biochemical syntheses, immunoassays and hybridization reactions. The matrix materials may additionally include fluophors or other luminescent moieties to produce luminescing matrices with memories. The memories include electronic and optical storage media and also include optical memories, such as bar codes and other machine-readable codes. By virtue of this combination, molecules and biological particles, such as phage and viral particles and cells, that are in proximity or in physical contact with the matrix combination can be labeled by programming the memory with identifying information and can be identified by retrieving the stored information. Combinations of matrix materials, memories, and linked molecules and biological materials are also provided.
    Type: Grant
    Filed: June 10, 1996
    Date of Patent: August 8, 2000
    Assignee: Irori
    Inventors: Michael P. Nova, Andrew E. Senyei, Hanan Potash
  • Patent number: 6017496
    Abstract: Combinations, called matrices with memories, of matrix materials that are encoded with an optically readable code are provided. The matrix materials are those that are used in as supports in solid phase chemical and biochemical syntheses, immunoassays and hybridization reactions. The matrix materials may additionally include fluophors or other luminescent moieties to produce luminescing matrices with memories. The memories include electronic and optical storage media and also include optical memories, such as bar codes and other machine-readable codes. By virtue of this combination, molecules and biological particles, such as phage and viral particles and cells, that are in proximity or in physical contact with the matrix combination can be labeled by programming the memory with identifying information and can be identified by retrieving the stored information. Combinations of matrix materials, memories, and linked molecules and biological materials are also provided.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: January 25, 2000
    Assignee: Irori
    Inventors: Michael P. Nova, Zahra Parandoosh, Andrew E. Senyei, Xiao-Yi Xiao, Gary S. David, Yozo Satoda, Chanfeng Zhao, Hanan Potash
  • Patent number: 5961923
    Abstract: Combinations, called matrices with memories, of matrix materials that are encoded with an optically readable code are provided. The matrix materials are those that are used in as supports in solid phase chemical and biochemical syntheses, immunoassays and hybridization reactions. The matrix materials may additionally include fluophors or other luminescent moieties to produce luminescing matrices with memories. The memories include electronic and optical storage media and also include optical memories, such as bar codes and other machine-readable codes. By virtue of this combination, molecules and biological particles, such as phage and viral particles and cells, that are in proximity or in physical contact with the matrix combination can be labeled by programming the memory with identifying information and can be identified by retrieving the stored information. Combinations of matrix materials, memories, and linked molecules and biological materials are also provided.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: October 5, 1999
    Assignee: Irori
    Inventors: Michael P. Nova, Zahra Parandoosh, Andrew E. Senyei, Xiao-Yi Xiao, Gary S. David, Yozo Satoda, Chanfeng Zhao, Hanan Potash
  • Patent number: 5296722
    Abstract: A memory cell includes a pair of spaced apart conductors on an insulating layer, and a novel electrically alterable resistive component between the conductors. This resistive component consists essentially of a single element semiconductor selected from the group of Si, Ge, C, and .alpha.-Sn, having a crystalline grain size which is smaller than polycrystalline. Dopant atoms in the semiconductor are limited to be less than 10.sup.17 atoms/CM.sup.3 ; and, such a doping range includes zero doping. All dopant atoms are interstitial in the semiconductor crystals and not substitutional.
    Type: Grant
    Filed: January 26, 1993
    Date of Patent: March 22, 1994
    Assignee: Unisys Corporation
    Inventors: Hanan Potash, Melvyn E. Genter, Bruce B. Roesner
  • Patent number: 5148256
    Abstract: In the disclosed computer, a plurality of register means for storing digital operands and control signals are in a semiconductor substrate; an arithmetic means for performing functional opertions on the operands are also in the substrate; an insulating layer covers the register means and the arithmetic means; and an interconnect matrix is on top of this insulating layer. The interconnect matrix includes pluralities of logic gates coupled through the insulating layer to the register means and arithmetic means and selectively interconnects them in response to the control signals.
    Type: Grant
    Filed: February 23, 1981
    Date of Patent: September 15, 1992
    Assignee: Unisys Corporation
    Inventors: Hanan Potash, Melvyn E. Genter, Bruce B. Roesner
  • Patent number: 4933735
    Abstract: Disclosed is a digital computer having memory means stacked on an insulating layer over a semiconductor substrate. In one embodiment, the memory means includes an array of diodes which overflies the substrate and generates control signals for an arithmetic section that lies in the substrate; and in another embodiment, the memory means includes N arrays of diodes which overlie the substrate and operate in parallel to generate signals representing arithmetic transformation of a portion of their address inputs.
    Type: Grant
    Filed: July 27, 1984
    Date of Patent: June 12, 1990
    Assignee: Unisys Corporation
    Inventors: Hanan Potash, Burton L. Levin, Bruce B. Roesner
  • Patent number: 4837730
    Abstract: In a computer which superpositions vector and scalar operations and in which operation results and operands are conducted between buffer registers and functional units on a bidirectional databus system, the result of one or more currently-executing scalar operations can be routed directly to the input of one or more functional units, bypassing the buffer registers and saving computer operational time. A scalar result is routed through a linking apparatus which directly connects a bidirectional databus path on which the scalar result is being conducted to a databus path on which a scalar operand is to be conducted. The routing is conditioned upon identity between the scalar result and operand and upon availability of a databus path to support the scalar operation. If the conditions are not met, the scalar result is conducted to the buffer registers, where it is held until needed or until a databus path is available.
    Type: Grant
    Filed: February 6, 1987
    Date of Patent: June 6, 1989
    Assignee: Scientific Computer Systems Corporation
    Inventors: Erick M. Cook, Andrew E. Phelps, Hanan Potash
  • Patent number: 4777615
    Abstract: A backplane structure for a computer includes first and second spaced apart backplane sections each having a series of spaced, vertical connector assemblies for receiving edge connectors of a series of parallel spaced apart circuit boards in a vertical orientation. Spaced bus lines run horizontally across each backplane section for interconnecting appropriate pins of the respective circuit board connectors. One of the backplane sections receives circuit boards of the memory section of a computer, and the other section receives the computer functional unit boards. A third backplane section extends between the first and second sections and has a series of spaced horizontal connector assemblies for receiving connector edges of a series of circuit boards in a horizontal orientation. At least some of the horizontal connector assemblies receive circuit boards of the buffer section of a computer.
    Type: Grant
    Filed: February 28, 1986
    Date of Patent: October 11, 1988
    Assignee: Scientific Computer Systems Corporation
    Inventor: Hanan Potash
  • Patent number: 4760518
    Abstract: A bi-directional databusing system is used in a computer that superposes vector and scalar operations. The computer consists of a main memory, a plurality of pipelined functional units, and a buffer for staging scalar and vector data objects between the main memory and the functional units. The busing system supports two-way data transfer during each of a succession of bus transfer cycles in which data is transferred to the buffer during one phase of a cycle, and from the buffer during a second cycle phase. The busing system includes three sets of bi-directional memory databuses, one for transferring scalar data objects between the main memory and buffer unit, and the other two for transferring vector data objects between the main memory and the buffer.
    Type: Grant
    Filed: February 28, 1986
    Date of Patent: July 26, 1988
    Assignee: Scientific Computer Systems Corporation
    Inventors: Hanan Potash, Erick M. Cook, Andrew E. Phelps, Mark A. Haakmeester, Jennifer S. Schuh, William B. Thompson
  • Patent number: 4744024
    Abstract: Disclosed is a data processing system which is comprised of a plurality of devices that carry on conversations with each other over a time-shared bus. These conversions can consist of a message from a device A to a device B which is immediately followed by a message from device B back to device A, or a message from device A to device B which is immediately followed by a message from device B to another device C, or a single message from device A to device B. In each case, the last device to receive a message assumes control of the bus; and it relinquishes this control by either sending a message to another device or by broadcasting a poll code to all devices on the bus.
    Type: Grant
    Filed: July 23, 1984
    Date of Patent: May 10, 1988
    Assignee: Burroughs Corporation
    Inventors: Hanan Potash, Melvyn E. Genter
  • Patent number: 4538241
    Abstract: An apparatus is disclosed that translates virtual memory addresses into physical memory addresses. In particular, this apparatus comprises a plurality of rows of content addressable memory cells, a corresponding plurality of random access memory cells and another corresponding plurality of control circuits. The content addressable memory cells store the virtual memory addresses and the random access memory cells store the physical memory addresses. The control circuits are coupled to both the content addressable and the random access memory cells and are disposed for controlling the operation of the apparatus.
    Type: Grant
    Filed: July 14, 1983
    Date of Patent: August 27, 1985
    Assignee: Burroughs Corporation
    Inventors: Burton L. Levin, Andrew E. Phelps, Hanan Potash
  • Patent number: 4467409
    Abstract: A flexible architecture for digital computers can be adapted to meet the many different functional requirements of several computer models. Each model includes an array of sequential logic units. These units include respective control memories for storing commands, means for sequentially fetching and executing selectable sequences of the commands, and soft functional structures for performing customized functions in response to the commands. Included within the soft functional structures are a plurality of selectable electrical contacts which customize the functional response of the structures to the commands. Except for these contacts and the content of the respective control memories, the units are substantially identical. All of the units in the array execute respective command sequences from their control memory to perform a single instruction for the computer model.
    Type: Grant
    Filed: August 5, 1980
    Date of Patent: August 21, 1984
    Assignee: Burroughs Corporation
    Inventors: Hanan Potash, Burton L. Levin, Melvyn E. Genter
  • Patent number: 4463423
    Abstract: Disclosed is a method of transforming an assignment statement of a high level programming language, such as ALGOL and COBOL, into first, second, and third sets of lower level object language instructions wherein instructions of the first set are executable in an interleaved fashion with instructions of the second and third sets, the latter two of which are executable at the same time. When the instructions of the first, second, and third sets are executed in the above-recited fashion, a substantial improvement in the execution time of the corresponding assignment statement is attained.
    Type: Grant
    Filed: July 14, 1982
    Date of Patent: July 31, 1984
    Assignee: Burroughs Corporation
    Inventors: Hanan Potash, Howard H. Green