Abstract: An integrated-circuit chip and method of operating said chip is provided. The integrated-circuit chip includes multiple processors, a system memory and a main system bus for carrying data between each of the processors and the system memory. The chip also has debug logic, a debug port for communicating with the debug logic from outside the chip and a debug connection that connects the debug logic to the main system bus. A power management system is also included for controlling the power supplied to each of a number of power domains on the chip. The debug logic and each of the processors are in different respective power domains. The debug logic is configured to send a debug instruction to any of the processors. The debug instruction is communicated over the debug connection and over the main system bus.

Abstract: A method of controlling an electronic device including a memory and a removable smart card. The method involves the device sending a request for context data to the smart card. The smart card sends context data to the device in response to the request and stores this data in the memory and power to the smart card is reduced. Power to the smart card is then increased or restored, and the data is written back to the smart card.

Abstract: An electronic device comprises a processor, a memory, a memory controller for controlling access to the memory, a hardware security module, and a bus system, to which the processor, the memory controller, and the hardware security module are connected. The hardware security module uses its connection to the bus system to detect requests on the bus system that are sent by the processor. The hardware security module has a secure state and a non-secure state. When in the secure state, the hardware security module adds a secure-state signal to requests sent by the processor over the bus system. The memory controller determines whether memory-access requests include the secure-state signal, and denies access to a secure region of the memory in response to receiving memory-access requests that do not include the secure-state signal.

Abstract: An integrated-circuit radio transmitter chip comprises a transmitter, a cryptographic engine and control circuitry for the cryptographic engine. The cryptographic engine performs a cryptographic operation by receiving input data, performing a first process to generate first result data and a second process to generate second result data. The first and second result data are used to generate output data. In response to determining that the transmitter is active, the control circuity controls the cryptographic engine to perform the first process and prevents the cryptographic engine from performing the second process while the transmitter is active. The control circuitry controls the cryptographic engine to perform the second process in response to determining that the transmitter is not active.

Abstract: An integrated circuit device has a processor, a software-trace message handling system, a software-trace message sink peripheral, and a hardware interconnect system. The interconnect system is capable of directing software-trace messages from the processor to the software-trace message handling system, and of directing software-trace messages from the processor to the software-trace message sink peripheral. The software-trace message sink peripheral can present an interconnect delay to the processor, when receiving a software-trace message from the processor, that is equal to or substantially equal to an interconnect delay that the software-trace message handling system would have presented to the processor if the software-trace message handling system were to have received the software-trace message.

Abstract: An integrated-circuit device comprising first and second radio systems. The first radio system comprises a first processor coupled to a first program memory and a first radio. The second radio system comprises a second processor coupled to a second program memory and a second radio. The device further comprises inter-processor communication (IPC) circuitry coupled to the first and second processors, for providing an IPC channel between the first and second processors. First software, stored in the first program memory for execution by the first processor comprises instructions for causing the first processor, in response to receiving a signal from the first radio, to send an electrical signal over the IPC channel to the second processor for causing second software stored in the second program memory to cause the second processor to send a command to the second radio.

Abstract: An electronic device comprises a processor operable at a variable processor privilege level and a memory comprising a secure memory area. A hardware module is operable at a variable module privilege level and is arranged to access the memory directly. The secure memory area is accessible by the hardware module only when the module privilege level exceeds a threshold value. The device has a first mode of operation in which said processor privilege level is higher than said threshold value and said module privilege level is lower than said threshold value. A controller is arranged, upon receiving a privilege promotion signal and the device being in the first mode, to move the device to a second mode wherein the module privilege level is higher than said threshold value.

Abstract: An electronic apparatus has a processor; a peripheral having a data interface and a data-attribute interface; a direct memory access (DMA) controller for the peripheral; a memory; a bus system connecting the processor, the DMA controller, and the memory; a data link between the DMA controller and the peripheral; and a data-attribute link between the DMA controller and the peripheral, separate from the data link. The DMA controller has data-transfer circuitry for transferring data between the memory and the data interface of the peripheral over the data link, and for transferring data-attribute information, associated with the data, between the memory and the data-attribute interface of the peripheral over the data-attribute link.

Abstract: A radio transceiver comprises one or more hardware resources, e.g. a processor; memory; a peripheral device; an algorithmic hardware accelerator; and/or a radio frequency component. A cellular communication radio is operable in an active mode in which it has access to the one or more hardware resources for transmitting and/or receiving cellular communication signals, and an inactive mode in which it does not. A global navigation satellite systems radio, arranged to use the one or more hardware resources to receive positioning signals, has access to the one or more hardware resources only when the cellular communication radio is operated in the inactive mode.

Abstract: An integrated circuit device has a processor, a software-trace message handling system, a software-trace message sink peripheral, and a hardware interconnect system. The interconnect system is capable of directing software-trace messages from the processor to the software-trace message handling system, and of directing software-trace messages from the processor to the software-trace message sink peripheral. The software-trace message sink peripheral can present an interconnect delay to the processor, when receiving a software-trace message from the processor, that is equal to or substantially equal to an interconnect delay that the software-trace message handling system would have presented to the processor if the software-trace message handling system were to have received the software-trace message.

Abstract: An electronic device comprises a processor, a memory, a memory controller for controlling access to the memory, a hardware security module, and a bus system, to which the processor, the memory controller, and the hardware security module are connected. The hardware security module uses its connection to the bus system to detect requests on the bus system that are sent by the processor. The hardware security module has a secure state and a non-secure state. When in the secure state, the hardware security module adds a secure-state signal to requests sent by the processor over the bus system. The memory controller determines whether memory-access requests include the secure-state signal, and denies access to a secure region of the memory in response to receiving memory-access requests that do not include the secure-state signal.

Abstract: An electronic device comprises a processor operable at a variable processor privilege level and a memory comprising a secure memory area. A hardware module is operable at a variable module privilege level and is arranged to access the memory directly. The secure memory area is accessible by the hardware module only when the module privilege level exceeds a threshold value. The device has a first mode of operation in which said processor privilege level is higher than said threshold value and said module privilege level is lower than said threshold value. A controller is arranged, upon receiving a privilege promotion signal and the device being in the first mode, to move the device to a second mode wherein the module privilege level is higher than said threshold value.

Abstract: A hardware cryptographic engine comprises a direct-memory-access (DMA) input module for receiving input data over a memory bus, and a cryptographic module. The cryptographic module comprises an input register having an input-register length, and circuitry configured to perform a cryptographic operation on data in the input register. The hardware cryptographic engine further comprises an input-alignment buffer having a length that is less than twice said input-register length, and alignment circuitry performing an alignment operation on input data in the input-alignment buffer. The hardware cryptographic engine is configured to pass input data, received by the DMA input module, from the memory bus to the input register of the cryptographic module after buffering an amount of input data no greater than the length of the input-alignment buffer.

Abstract: An electronic apparatus has a processor; a peripheral having a data interface and a data-attribute interface; a direct memory access (DMA) controller for the peripheral; a memory; a bus system connecting the processor, the DMA controller, and the memory; a data link between the DMA controller and the peripheral; and a data-attribute link between the DMA controller and the peripheral, separate from the data link. The DMA controller has data-transfer circuitry for transferring data between the memory and the data interface of the peripheral over the data link, and for transferring data-attribute information, associated with the data, between the memory and the data-attribute interface of the peripheral over the data-attribute link.

Abstract: A method of controlling an electronic device including a memory and a removable smart card. The method involves the device sending a request for context data to the smart card. The smart card sends context data to the device in response to the request and stores this data in the memory and power to the smart card is reduced. Power to the smart card is then increased or restored, and the data is written back to the smart card.

Abstract: A radio transceiver comprises one or more hardware resources, e.g. a processor; memory; a peripheral device; an algorithmic hardware accelerator; and/or a radio frequency component. A cellular communication radio is operable in an active mode in which it has access to the one or more hardware resources for transmitting and/or receiving cellular communication signals, and an inactive mode in which it does not. A global navigation satellite systems radio, arranged to use the one or more hardware resources to receive positioning signals, has access to the one or more hardware resources only when the cellular communication radio is operated in the inactive mode.

Abstract: A radio frequency transceiver device comprises a control register unit including one or more registers and a central processing unit arranged to access the one or more registers via a memory bus. The device also comprises a sequencer module comprising one or more configuration registers connected to the central processing unit via a control bus and also comprises one or more trigger inputs. A sequencer memory module is connected to the sequencer module and is arranged to store one or more read/write commands comprising instructions to read from and/or write to the registers within the control register unit. The sequencer module is arranged such that upon receiving a trigger event via at least one of the one or more trigger inputs, it executes the one or more read/write commands.

Abstract: A radio frequency transceiver device comprises a control register unit including one or more registers and a central processing unit arranged to access the one or more registers via a memory bus. The device also comprises a sequencer module comprising one or more configuration registers connected to the central processing unit via a control bus and also comprises one or more trigger inputs. A sequencer memory module is connected to the sequencer module and is arranged to store one or more read/write commands comprising instructions to read from and/or write to the registers within the control register unit. The sequencer module is arranged such that upon receiving a trigger event via at least one of the one or more trigger inputs, it executes the one or more read/write commands.

Abstract: The present publication describes a heat-resistant optical layered structure, a manufacturing method for a layered structure, and the use of a layered structure as a detector, emitter, and reflecting surface. The layered structure comprises a reflecting layer, an optical structure on top of the reflecting layer, and preferably shielding layers for shielding the reflecting layer and the optical structure. According to the invention, the optical structure on top of the reflecting layer comprises at least one partially transparent layer, which is optically fitted at a distance to the reflecting layer.

Abstract: The present publication describes a heat-resistant optical layered structure, a manufacturing method for a layered structure, and the use of a layered structure as a detector, emitter, and reflecting surface. The layered structure comprises a reflecting layer, an optical structure on top of the reflecting layer, and preferably shielding layers for shielding the reflecting layer and the optical structure. According to the invention, the optical structure on top of the reflecting layer comprises at least one partially transparent layer, which is optically fitted at a distance to the reflecting layer.