Abstract: Techniques are disclosed for utilizing a non-ported generic device (NGD) or other non-ported hardware to couple processing device(s) to access components on a serial data bus without the need for integrated manager hardware. Using the NGD, a processing device(s) can utilize available unused bandwidth on the serial data bus to communicate with components coupled with the serial data bus, including a processing device having the manager hardware. Various alterations and embodiments are disclosed.

Abstract: A method, an apparatus, and a computer program product for communication within a wireless terminal. The method can be implemented using dedicated logic and managed and controlled by state machines and/or sequencers. Data received or provided in a memory of a first integrated circuit of a terminal is encoded and transmitted in a data packet to a second integrated circuit. A header identifying the data type and providing a destination is included in the data packet. The destination may be identified as a memory address memory of the second integrated circuit that is mapped to a corresponding memory address of the first integrated circuit at which the data is received. In an aspect, the apparatus receives a header, detects an error in the received header, determines a failure to identify a packet boundary when the error is detected, and performs a search operation to identify the packet boundary.

Abstract: A bus interface device is configured to receive data from one or more devices via a bus. The bus interface device is also configured to process first data received via the bus according to a transport protocol of the bus. The bus interface device is further configured to process second data received via the bus according to a native coding/decoding (CODEC) protocol that is distinct from the transport protocol.

Abstract: A method for classifying radio frequency front-end (RFFE) devices. The method includes enumerating a radio frequency front-end (RFFE) slave device according to at least one classifier bit within the RFFE slave device. The method also includes adjusting an RFFE control interface of an RFFE master device according to slave device configuration information determined from the at least one classifier bit within the RFFE slave device.

Abstract: An apparatus including dual physical layer transceivers for high speed synchronous interface (HSI) frame interleaving. The apparatus includes a first physical layer transceiver and a second physical layer transceiver. The apparatus further includes a frame interleaver that is communicably coupled to each of the first and second physical layer transceivers. The frame interleaver is operable to interleave a protocol data unit (PDU) of high speed synchronous interface (HSI) frames across uplink lanes of the first physical layer transceiver and uplink lanes of the second physical layer transceiver according to a pipe offset.

Abstract: An embedded communication terminal equipped with an interface device which performs security tasks, driver tasks, power management tasks and handover tasks, and thus relieves the application processor of the embedded communication terminal.

Abstract: Methods, systems, apparatuses, and computer-readable media for controlling components connected to and/or otherwise associated with a data bus are presented. According to one or more aspects of the disclosure, a plurality of processing devices having data bus management capability and at least one data bus associated with the plurality of processing devices may be identified. Subsequently, an inter-processor communication (IPC) layer for communication between the plurality of processing devices and the at least one data bus may be established over a messaging layer utilized by the at least one data bus. At least one component associated with the at least one data bus may then be controlled via the IPC layer using at least one of the plurality of processing devices.

Abstract: Arrangements for restarting data transmission on a serial low-power inter-chip media bus (SLIMbus) are presented. A clock signal may be provided in an active mode to a component communicatively coupled with the SLIMbus. Immediately prior to the clock signal in the active mode being provided, the clock signal may have been in a paused mode. While the clock signal was in the paused mode at least until the clock signal is provided in the active mode, the data line may have been inactive (e.g., a toggle on the data line may not have been present). Frame synchronization data for a frame may be transmitted. The frame synchronization data for the frame, as received by the component, may not match expected frame synchronization data. Payload data may be transmitted as part of the frame to the component, wherein the payload data is expected to be read properly by the component.

Abstract: Techniques are disclosed for utilizing a non-ported generic device (NGD) or other non-ported hardware to couple processing device(s) to access components on a serial data bus without the need for integrated manager hardware. Using the NGD, a processing device(s) can utilize available unused bandwidth on the serial data bus to communicate with components coupled with the serial data bus, including a processing device having the manager hardware. Various alterations and embodiments are disclosed.

Abstract: A bus interface device is configured to receive data from one or more devices via a bus. The bus interface device is also configured to process first data received via the bus according to a transport protocol of the bus. The bus interface device is further configured to process second data received via the bus according to a native coding/decoding (CODEC) protocol that is distinct from the transport protocol.

Abstract: Techniques for mapping applications to radios in a wireless communication device are described. In one design, a controller residing below an operating system may receive inputs from applications residing above the operating system. The controller may determine radios selected based on the application inputs and further to mitigate interference between these radios. The controller may determine mapping of the applications to the radios based on the application inputs and may provide, to the applications, information indicative of the radios to which the applications are mapped. The applications may obtain connectivity via their selected radios. The controller may interface with entities in both upper layers and lower layers to facilitate radio selection and application-to-radio mapping.

Abstract: Systems and methodologies are described herein that facilitate an asynchronous bus architecture for multi-radio coexistence associated with a wireless device. As described herein, a system of buses operating in an asynchronous manner, combined with optional on-chip and/or other supplemental buses, can be utilized to couple respective radios and/or other related endpoints to a coexistence management platform, thereby facilitating management of coexistence between multiple radios in a unified and scalable manner. As further described herein, communication between a coexistence manager and its respective managed endpoints can be facilitated through the use of a single bus or multiple buses that can be switched and/or otherwise operate in a concurrent manner to facilitate expedited conveyance of radio event notifications and their corresponding responses.

Abstract: Systems and methodologies are described herein that facilitate a synchronous bus architecture for multi-radio coexistence associated with a wireless device. As described herein, a system of buses operating in a synchronous manner, combined with optional on-chip and/or other supplemental buses, can be utilized to couple respective radios and/or other related endpoints to a coexistence management platform, thereby facilitating management of coexistence between multiple radios in a unified and scalable manner. As further described herein, communication between a coexistence manager and its respective managed endpoints can be facilitated through the use of a single bus or multiple buses (e.g., external buses, on-chip and/or other internal buses, etc.) that can operate concurrently and/or in an otherwise cooperative manner to facilitate expedited conveyance of radio event notifications and their corresponding responses.

Abstract: Systems and methodologies are described herein that facilitate implementation and use of a sleep mode for a multi-radio coexistence manager. As described herein, respective radios coordinated by a coexistence manager (CxM) can be grouped into radio or sleep clusters, for which the CxM can enter a low-power mode (e.g., a sleep mode) based on respective operating states of radios in the clusters. As further described herein, a CxM can provide an acquisition sequence and/or other suitable means to enable respective radios to synchronize with the CxM. In addition, techniques are provided herein by which a CxM can indicate its present operating mode (e.g., active, wakeable sleep, non-wakeable sleep, or disabled) to respective radios, and by which a radio can wake the CxM from a sleep operating mode under predetermined circumstances.

Abstract: A multiprocessor system comprises a first processor (P1) and a second processor (P2) each having an input/output set up for the connection of a tightly coupled semiconductor memory. Furthermore, the multiprocessor system comprises a shared tightly coupled integrated semiconductor memory (101), which can be accessed by both processors (P1, P2) via their input/output.

Abstract: A computer device having a plurality of system components which access a common memory. For memory access, a common buffer store is provided which increases access and can be matched to the memory.

Abstract: The present invention provides an apparatus for controlling access, by processing devices to memories in an embedded system, with the apparatus being arranged between the processing devices and the memories, and with the apparatus independently moving data between the memories and between the memories and internal memories in the processing devices.

Abstract: A multiprocessor system comprises a first processor (P1) and a second processor (P2) each having an input/output set up for the connection of a tightly coupled semiconductor memory. Furthermore, the multiprocessor system comprises a shared tightly coupled integrated semiconductor memory (101), which can be accessed by both processors (P1, P2) via their input/output.

Abstract: In a digital signal processor, a file address table (FAT) file is stored in the storage memory unit of the digital signal processor rather than in the program memory of the central processing unit. When a selected file is to be processed, a summary file is generated in the stack sector of the program memory, the summary file including the FAT file entries for the selected file. By positioning the FAT files in this manner, not only are locations in the program memory made available for the storage of other files, but the performance of the digital signal processor can be enhanced.