Patents by Inventor Hans-Joachim L. Gossmann

Hans-Joachim L. Gossmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10483355
    Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: November 19, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Matthias Bauer, Hans-Joachim L. Gossmann, Benjamin Colombeau
  • Patent number: 10381465
    Abstract: A method of forming an asymmetrical three dimensional semiconductor device. The method may include providing a fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the fin structure comprises a first end surface not covered by the gate structure and second end surface not covered by the gate structure. The method may further include directing ions in a fin treatment to the fin structure, wherein the fin treatment comprises a first treatment of the first end surface and a second treatment of the second end surface different from the first treatment.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 13, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Shiyu Sun, Naomi Yoshida, Benjamin Colombeau, Hans-Joachim L. Gossmann
  • Publication number: 20180240893
    Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.
    Type: Application
    Filed: October 24, 2017
    Publication date: August 23, 2018
    Inventors: Matthias BAUER, Hans-Joachim L. GOSSMANN, Benjamin COLOMBEAU
  • Publication number: 20180069100
    Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.
    Type: Application
    Filed: October 24, 2017
    Publication date: March 8, 2018
    Inventors: Matthias BAUER, Hans-Joachim L. GOSSMANN, Benjamin COLOMBEAU
  • Patent number: 9748364
    Abstract: A method for forming a three dimensional device. The method may include directing ions to an end surface of an extension region of a fin structure, the fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein the ions have trajectories extending in a plane perpendicular to the substrate plane and parallel to the fin axis, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the end surface is not covered by the gate structure.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: August 29, 2017
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Shiyu Sun, Naomi Yoshida, Benjamin Colombeau, Hans-Joachim L. Gossmann
  • Publication number: 20160315177
    Abstract: A method of forming an asymmetrical three dimensional semiconductor device. The method may include providing a fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the fin structure comprises a first end surface not covered by the gate structure and second end surface not covered by the gate structure. The method may further include directing ions in a fin treatment to the fin structure, wherein the fin treatment comprises a first treatment of the first end surface and a second treatment of the second end surface different from the first treatment.
    Type: Application
    Filed: September 18, 2015
    Publication date: October 27, 2016
    Inventors: Shiyu Sun, Naomi Yoshida, Benjamin Colombeau, Hans-Joachim L. Gossmann
  • Publication number: 20160315176
    Abstract: A method for forming a three dimensional device. The method may include directing ions to an end surface of an extension region of a fin structure, the fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein the ions have trajectories extending in a plane perpendicular to the substrate plane and parallel to the fin axis, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the end surface is not covered by the gate structure.
    Type: Application
    Filed: June 19, 2015
    Publication date: October 27, 2016
    Inventors: Shiyu Sun, Naomi Yoshida, Benjamin Colombeau, Hans-Joachim L. Gossmann
  • Patent number: 9455335
    Abstract: A method of forming a fin field effect transistor (finFET) device includes forming a fin structure on a substrate, the substrate comprising a semiconductor material and forming a replacement gate cavity comprising an exposed portion of the fin structure and a sidewall portion adjacent the exposed portion, wherein the exposed portion of the fin structure defines a channel region. The method further includes performing at least one implant into the exposed portion of the fin structure.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: September 27, 2016
    Assignee: Varian Semiconductor Equiment Associates, Inc
    Inventors: Anthony Renau, Hans-Joachim L. Gossmann
  • Patent number: 9455196
    Abstract: A method of processing a workpiece to create a doped fin structure is disclosed. A portion of the workpiece is subjected to a pre-amorphizing implant to create an amorphized region. This amorphized region is then implanted with dopant species, at an implant energy and dose so that the dopant species are contained within the amorphized region. The doped amorphized region is then subjected to a laser melt anneal which crystallizes the amorphized region. The dopant profile is box-like, and the dopant is confined to the previously amorphized region.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: September 27, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nilay A. Pradhan, Benjamin Colombeau, Hans-Joachim L. Gossmann
  • Publication number: 20160133523
    Abstract: A method of processing a workpiece to create a doped fin structure is disclosed. A portion of the workpiece is subjected to a pre-amorphizing implant to create an amorphized region. This amorphized region is then implanted with dopant species, at an implant energy and dose so that the dopant species are contained within the amorphized region. The doped amorphized region is then subjected to a laser melt anneal which crystallizes the amorphized region. The dopant profile is box-like, and the dopant is confined to the previously amorphized region.
    Type: Application
    Filed: November 6, 2015
    Publication date: May 12, 2016
    Inventors: Nilay A. Pradhan, Benjamin Colombeau, Hans-Joachim L. Gossmann
  • Publication number: 20150132907
    Abstract: A method of forming a fin field effect transistor (finFET) device includes forming a fin structure on a substrate, the substrate comprising a semiconductor material and forming a replacement gate cavity comprising an exposed portion of the fin structure and a sidewall portion adjacent the exposed portion, wherein the exposed portion of the fin structure defines a channel region. The method further includes performing at least one implant into the exposed portion of the fin structure.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Anthony Renau, Hans-Joachim L. Gossmann
  • Patent number: 5500391
    Abstract: A process for making a MOS device on a silicon substrate includes the step of forming a buried layer of germanium-silicon alloy in the substrate, or, alternatively, a buried layer of silicon enclosed between thin, germanium-rich layers. This buried layer is doped with boron, and tends to confine the boron during annealing and oxidation steps. The process includes a step of exposing the substrate to an oxidizing atmosphere such that an oxide layer 10 .ANG.-500 .ANG. thick is grown on the substrate.
    Type: Grant
    Filed: August 9, 1994
    Date of Patent: March 19, 1996
    Assignee: AT&T Corp.
    Inventors: Joze Bevk, Leonard C. Feldman, Hans-Joachim L. Gossmann, Henry S. Luftman, Ran-Hong Yan
  • Patent number: 5169798
    Abstract: Disclosed is a method of making a semiconductor device that comprises MBE at substrate temperatures substantially lower than conventionally used temperatures. A significant aspect of the method is the ability to produce highly doped (e.g., 10.sup.19 cm.sup.-3) epitaxial single crystal Si layers. The deposition can be carried out such that substantially all (at least 90%) dopant atoms are electrically active at 20.degree. C. However, the method is not limited to Si MBE. Exemplarily, the method can be used to produce epitaxial single crystal GaAs having very short (e.g., <100ps) carrier lifetime. Such material can be useful for, e.g., high speed photodetectors. Incorporation into the method of a relatively low temperature rapid thermal anneal makes possible low temperature MBE growth of relatively thick semiconductor layers.
    Type: Grant
    Filed: June 28, 1990
    Date of Patent: December 8, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: David J. Eaglesham, Hans-Joachim L. Gossmann