Patents by Inventor Hans-Joachim Ludwig Gossmann

Hans-Joachim Ludwig Gossmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9853129
    Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: December 26, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Matthias Bauer, Hans-Joachim Ludwig Gossmann, Benjamin Colombeau
  • Publication number: 20170330960
    Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.
    Type: Application
    Filed: August 19, 2016
    Publication date: November 16, 2017
    Inventors: Matthias BAUER, Hans-Joachim Ludwig GOSSMANN, Benjamin COLOMBEAU
  • Patent number: 6632728
    Abstract: We have found that under certain prescribed conditions a co-implantation process can be effective in increasing the electrical activation of implanted dopant ions. In accordance with one aspect of our invention, a method of making a semiconductor device includes the steps of providing a single crystal semiconductor body, implanting vacancy-generating, ions into a preselected region of the body, implanting dopant ions into the preselected region, the dopant implant forming interstitial defects in the body, and annealing the body to electrically activate the dopant ions. Importantly, in our method the vacancy-generating implant introduces vacancy defects into the preselected region that are effective to annihilate the interstitial defects. In addition, process steps that amorphize the surface of the implanted region are avoided, and the dose of the vacancy-generating implant is made to be greater than that of the dopant implant.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: October 14, 2003
    Assignee: Agere Systems Inc.
    Inventors: Hans-Joachim Ludwig Gossmann, Conor Stefan Rafferty, Tony E. Haynes, Ramki Kalyanaraman, Vincent C. Venezia, Maria Lourdes Pelaz-Montes
  • Publication number: 20030013260
    Abstract: We have found that under certain prescribed conditions a co-implantation process can be effective in increasing the electrical activation of implanted dopant ions. In accordance with one aspect of our invention, a method of making a semiconductor device includes the steps of providing a single crystal semiconductor body, implanting vacancy-generating ions into a preselected region of the body, implanting dopant ions into the preselected region, the dopant implant forming interstitial defects in the body, and annealing the body to electrically activate the dopant ions. Importantly, in our method the vacancy-generating implant introduces vacancy defects into the preselected region that are effective to annihilate the interstitial defects. In addition, process steps that amorphize the surface of the implanted region are avoided, and the dose of the vacancy-generating implant is made to be greater than that of the dopant implant.
    Type: Application
    Filed: July 16, 2001
    Publication date: January 16, 2003
    Inventors: Hans-Joachim Ludwig Gossmann, Conor Stefan Rafferty, Tony E. Haynes, Ramki Kalyanaraman, Vincent C. Venezia, Maria Lourdes Pelaz-Montes
  • Patent number: 6403454
    Abstract: We have discovered that, contrary to conventional wisdom about forming DP defects, electrical saturation in highly doped 2D layers of Si does not occur. In accordance with one aspect of our invention, free-carrier concentrations in excess of about 7×1020 cm−3 can be attained in single crystal Si layers &dgr;-doped with a Group V element. In one embodiment, free-carrier concentrations in excess of about 2×1021 cm−3 are realized in single crystal Si that is &dgr;-doped with Sb. In another embodiment, the &dgr;-doped layer is formed as an integral part of an FET.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: June 11, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Paul H. Citrin, Hans-Joachim Ludwig Gossmann, David Anthony Muller
  • Patent number: 6358824
    Abstract: A method of fabricating an IC comprises the steps of: (a) forming trench isolation regions in a surface of a semiconductor body; and (b) forming a tub-tie region between at least one pair of the trench isolation regions (when viewed in cross-section) by a process that includes the following steps: (b1) forming a first photolithographic mask that covers and is in registration with the tub-tie region; (b2) implanting ions of a first conductivity-type to form a tub region adjacent the tub-tie region; (b3) removing the first mask; (b4) forming a second photolithographic mask that has an opening that exposes most of the underlying tub-tie region but overlaps a first peripheral section on one side of the tub-tie region; (b5) implanting ions to form a pedestal portion of a second conductivity-type within the tub-tie region; and (b6) implanting ions of the first conductivity-type at an acute (preferably non-zero) angle −⊕ with respect to the normal to the surface to the body so as to form a conductivity-t
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: March 19, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Hans-Joachim Ludwig Gossmann, Thi-Hong-Ha Vuong
  • Patent number: 6153920
    Abstract: A semiconductor device having a carbon-containing region with an advantageous concentration profile is disclosed. The carbon is introduced into a region of the substrate and at a depth below the space-charge layer of the device and at a concentration such that the carbon atoms absorb point defects created in the substrate during device fabrication but do not adversely affect the leakage characteristics of the device.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: November 28, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Hans-Joachim Ludwig Gossmann, Conor Stefan Rafferty
  • Patent number: 6054342
    Abstract: An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC tub-ties of this design are provided for both NMOS and PMOS transistors. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: April 25, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Hans-Joachim Ludwig Gossmann, Thi-Hong-Ha Vuong
  • Patent number: 6043139
    Abstract: Diffusion of ion-implanted dopant is controlled by incorporating electrically inactive impurity in a semiconductor layer by at least one crystal growth technique.
    Type: Grant
    Filed: November 28, 1995
    Date of Patent: March 28, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: David James Eaglesham, Hans-Joachim Ludwig Gossmann, John Milo Poate, Peter Adriaan Stolk
  • Patent number: 5949112
    Abstract: An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC tub-ties of this design are provided for both NMOS and PMOS transistors. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: September 7, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Hans-Joachim Ludwig Gossmann, Thi-Hong-Ha Vuong
  • Patent number: 5731626
    Abstract: Diffusion of ion-implanted dopant is controlled by incorporating electrically inactive impurity in a semiconductor layer by at least one crystal growth technique.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: March 24, 1998
    Assignee: Lucent Technologies Inc.
    Inventors: David James Eaglesham, Hans-Joachim Ludwig Gossmann, John Milo Poate, Peter Adriaan Stolk