Patents by Inventor Hans-Joachim Schulze

Hans-Joachim Schulze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220029013
    Abstract: A method for fabricating a semiconductor device includes: forming a trench in a first major surface of a semiconductor body having a first conductivity type; forming a gate in the trench; forming a body region of a second conductivity type in the semiconductor body; implanting a second dopant species into a first region of the body region and a first dopant species into a second region of the body region, the first dopant species providing the first conductivity type, the second dopant species being different from the first dopant species and reducing the diffusion of the first dopant species in the semiconductor body; and thermally annealing the semiconductor body to form a source region that includes the first and second dopant species, and to produce a pn-junction between the source and body regions at a depth dpn from the first major surface, wherein 50 nm<dpn<300 nm.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 27, 2022
    Inventors: Anton Mauder, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder
  • Publication number: 20220013625
    Abstract: A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a semiconductor body including a semiconductor substrate and a semiconductor layer on the semiconductor substrate. The semiconductor body has a first main surface and a second main surface opposite to the first main surface along a vertical direction. The vertical power semiconductor device further includes a drift region in the semiconductor body. A first part of the drift region is arranged in the semiconductor substrate. A second part of the drift region is arranged in the semiconductor layer. The vertical power semiconductor device further includes a field stop region arranged in the semiconductor substrate, wherein a doping concentration of the field stop region averaged along the vertical direction is larger than a doping concentration of the drift region averaged along the vertical direction.
    Type: Application
    Filed: July 8, 2021
    Publication date: January 13, 2022
    Inventors: Hans-Joachim Schulze, Philipp Kohler-Redlich, Thomas Laska, Franz-Josef Niedernostheide, Vera van Treek
  • Patent number: 11195695
    Abstract: An ion implantation method includes changing an ion acceleration energy and/or an ion beam current density of an ion beam while effecting a relative movement between a semiconductor substrate and the ion beam impinging on a surface of the semiconductor substrate.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: December 7, 2021
    Assignee: Infineon Technologies AG
    Inventors: Moriz Jelinek, Michael Brugger, Hans-Joachim Schulze, Werner Schustereder, Peter Zupan
  • Publication number: 20210376068
    Abstract: A method of forming a semiconductor device includes forming a trench in a semiconductor body; at least partially filling the trench with a filling material; introducing dopants into a portion of the filling material; and applying a first thermal processing to the semiconductor body to spread the dopants in the filling material along a vertical direction of the filling material by a diffusion process. The vertical doping profile of the dopants within the doped filling material is shaped during the first thermal processing. Additionally, the dopants are substantially confined to within the trench and substantially do not diffuse from the doped filling material into the semiconductor body during the first thermal processing. A second thermal processing is applied to the semiconductor body after the first thermal processing to cause diffusion of the dopants from the doped filling material into the semiconductor body adjoining the trench.
    Type: Application
    Filed: August 17, 2021
    Publication date: December 2, 2021
    Applicant: Infineon Technologies AG
    Inventors: Reinhard PLOSS, Hans-Joachim SCHULZE
  • Publication number: 20210359087
    Abstract: A method of forming a semiconductor device and a semiconductor device are provided. The method includes forming a graphene layer at a first side of a silicon carbide substrate having at least next to the first side a first defect density of at most 5*102/cm2; attaching an acceptor layer at the graphene layer to form a wafer-stack, the acceptor layer comprising silicon carbide having a second defect density higher than the first defect density; forming an epitaxial silicon carbide layer; splitting the wafer-stack along a split plane in the silicon carbide substrate to form a device wafer comprising the graphene layer and a silicon carbide split layer at the graphene layer; and further processing the device wafer at the upper side.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 18, 2021
    Inventors: Hans-Joachim Schulze, Roland Rupp
  • Publication number: 20210351077
    Abstract: A method for processing a wide band gap semiconductor wafer includes: depositing a support layer including semiconductor material at a back side of a wide band gap semiconductor wafer, the wide band gap semiconductor wafer having a band gap larger than the band gap of silicon; depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer; and splitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer comprising at least a part of the epitaxial layer, and a remaining wafer comprising the support layer.
    Type: Application
    Filed: July 22, 2021
    Publication date: November 11, 2021
    Inventors: Francisco Javier Santos Rodriguez, G√ľnter Denifl, Tobias Hoechbauer, Martin Huber, Wolfgang Lehnert, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 11171230
    Abstract: In an embodiment, a semiconductor device is provided. The semiconductor device includes: a semiconductor body of a first conductivity type having opposing first and second major surfaces; a gate arranged in a trench extending into the semiconductor body from the first major surface; a body region of a second conductivity type; a source region of the first conductivity type arranged on the body region and having first and second dopant species. The source region forms a pn-junction with the body junction, the pn-junction being arranged at a depth dpn from the first major surface, wherein 50 nm<dpn<300 nm. A drain region of the first conductivity type is arranged in the semiconductor body under the trench.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: November 9, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder
  • Publication number: 20210343835
    Abstract: A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.
    Type: Application
    Filed: July 14, 2021
    Publication date: November 4, 2021
    Inventors: Ralf Siemieniec, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Rudolf Elpelt, Romain Esteve, Michael Hell, Daniel Kueck, Caspar Leendertz, Dethard Peters, Hans-Joachim Schulze
  • Patent number: 11158707
    Abstract: A transistor device may include a semiconductor body, a plurality of cell regions each comprising a plurality of transistor cells that are at least partially integrated in the semiconductor body and that each comprise a respective gate electrode, a plurality of routing channels each arranged between two or more of the cell regions, a gate pad arranged above a first surface of the semiconductor body, and a plurality of gate runners each coupled to the gate pad and each arranged in one of the plurality of routing channels. Each of the plurality of gate runners may be associated with one of the plurality of cell regions such that the gate electrodes in each of the plurality of cell regions are connected to an associated gate runner, and each of the plurality of routing channels comprises two or more gate runners that are routed in parallel and spaced apart.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: October 26, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hanno Melzner, Markus Dankerl, Peter Irsigler, Sebastian Schmidt, Hans-Joachim Schulze
  • Publication number: 20210320174
    Abstract: A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction. The vertical power semiconductor device further includes a drift region in the semiconductor body. The drift region includes platinum atoms. The vertical power semiconductor device further includes a field stop region in the semiconductor body between the drift region and the second main surface. The field stop region includes a plurality of impurity peaks. A first impurity peak of the plurality of impurity peaks has a larger concentration than a second impurity peak of the plurality of impurity peaks. The first impurity peak includes hydrogen and the second impurity peak includes helium.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 14, 2021
    Inventors: Hans-Joachim Schulze, Christian Jaeger, Moriz Jelinek, Daniel Schloegl, Benedikt Stoib
  • Patent number: 11139369
    Abstract: A method of forming a semiconductor device includes forming a trench in a semiconductor body; at least partially filling the trench with a filling material, the filling material; introducing dopants into a portion of the filling material, where the dopants have a first diffusion coefficient relative to the filling material and have a second diffusion coefficient relative to the semiconductor body, where the first diffusion coefficient is greater than the second diffusion coefficient, and where a ratio of the first diffusion coefficient to the second diffusion coefficient is greater than 10; and applying thermal processing to the semiconductor body configured to spread the dopants in the filling material along a vertical direction between a bottom side and a top side of the filling material by a diffusion process.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 5, 2021
    Inventors: Reinhard Ploss, Hans-Joachim Schulze
  • Patent number: 11121242
    Abstract: A method is provided for operating a semiconductor device which includes an IGBT having a desaturation semiconductor structure connected to a first electrode terminal and a gate electrode terminal for controlling a desaturation channel. The method includes: applying a first gate voltage to the gate electrode terminal so that current flows through the IGBT between the first electrode terminal and a second electrode terminal and current flow through the desaturation channel is substantially blocked; applying a different second gate voltage to the gate electrode terminal so that current flows through the IGBT between the first and second electrode terminals and charge carriers flow as a desaturating current through the desaturation channel to the first electrode terminal; and applying a different third gate voltage to the gate electrode terminal so that current flow through the IGBT between the first and second electrode terminals is substantially blocked.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: September 14, 2021
    Assignee: Infineon Technologies AG
    Inventors: Johannes Laven, Hans-Joachim Schulze
  • Publication number: 20210272843
    Abstract: A power semiconductor device includes: first and second trenches extending from a surface of a semiconductor body along a vertical direction and laterally confining a mesa region along a first lateral direction; source and body regions in the mesa region electrically connected to a first load terminal; and a first insulation layer having a plurality of insulation blocks, two of which laterally confine a contact hole. The first load terminal extends into the contact hole to contact the source and body regions at the mesa region surface. A first insulation block laterally overlaps with the first trench. A second insulation block laterally overlaps with the second trench. The first insulation block has a first lateral concentration profile of a first implantation material of the source region along the first lateral direction that is different from a corresponding second lateral concentration profile for the second insulation block.
    Type: Application
    Filed: May 20, 2021
    Publication date: September 2, 2021
    Inventors: Markus Beninger-Bina, Matteo Dainese, Ingo Dirnstorfer, Erich Griebl, Johannes Georg Laven, Anton Mauder, Hans-Joachim Schulze
  • Patent number: 11107893
    Abstract: A method of forming a semiconductor device and a semiconductor device are provided. The method includes forming a graphene layer at a first side of a silicon carbide substrate having at least next to the first side a first defect density of at most 500/cm2. An acceptor layer is attached at the graphene layer to form a wafer-stack. The acceptor layer includes silicon carbide having a second defect density higher than first defect density. The wafer-stack is split along a split plane in the silicon carbide substrate to form a device wafer including the graphene layer and a silicon carbide split layer at the graphene layer. An epitaxial silicon carbide layer extending to an upper side of the device wafer is formed on the silicon carbide split layer. The device wafer is further processed at the upper side.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: August 31, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Roland Rupp
  • Patent number: 11107732
    Abstract: A method for processing a wide band gap semiconductor wafer is proposed. The method includes depositing a non-monocrystalline support layer at a back side of a wide band gap semiconductor wafer, depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer, and splitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer including at least a part of the epitaxial layer, and a remaining wafer including the non-monocrystalline support layer.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: August 31, 2021
    Assignee: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Guenter Denifl, Tobias Franz Wolfgang Hoechbauer, Martin Huber, Wolfgang Lehnert, Roland Rupp, Hans-Joachim Schulze
  • Publication number: 20210265468
    Abstract: A semiconductor device includes a semiconductor substrate having a first dopant and a second dopant. A covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent atomic radius of the second dopant. The semiconductor device further includes a semiconductor layer on the semiconductor substrate and semiconductor device elements in the semiconductor layer. A vertical concentration profile of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate and the semiconductor layer to a surface of the semiconductor substrate opposite to the interface.
    Type: Application
    Filed: April 21, 2021
    Publication date: August 26, 2021
    Inventors: Ingo Muri, Johannes Konrad Baumgartl, Oliver Hellmund, Jacob Tillmann Ludwig, Iris Moder, Thomas Neidhart, Gerhard Schmidt, Hans-Joachim Schulze
  • Publication number: 20210265484
    Abstract: A method includes providing a layer of porous silicon carbide supported by a silicon carbide substrate, providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide, forming a plurality of semiconductor devices in the layer of epitaxial silicon carbide, and separating the substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. Additional methods are described.
    Type: Application
    Filed: May 7, 2021
    Publication date: August 26, 2021
    Inventors: Hans-Joachim Schulze, Roland Rupp, Francisco Javier Santos Rodriguez
  • Patent number: 11101343
    Abstract: A semiconductor component has a gate structure that extends from a first surface into an SiC semiconductor body. A body area in the SiC semiconductor body adjoins a first side wall of the gate structure. A first shielding area and a second shielding area of the conductivity type of the body area have at least twice as high a level of doping as the body area. A diode area forms a Schottky contact with a load electrode between the first shielding area and the second shielding area.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: August 24, 2021
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Rudolf Elpelt, Romain Esteve, Michael Hell, Daniel Kueck, Caspar Leendertz, Dethard Peters, Hans-Joachim Schulze
  • Publication number: 20210257489
    Abstract: A semiconductor component includes a semiconductor body having opposing first surface and second surfaces, and a side surface surrounding the semiconductor body. The semiconductor component also includes an active region including a first semiconductor region of a first conductivity type, which is electrically contacted via the first surface, and a second semiconductor region of a second conductivity type, which is electrically contacted via the second surface. The semiconductor component further includes an edge termination region arranged in a lateral direction between the first semiconductor region of the active region and the side surface, and includes a first edge termination structure and a second edge termination structure. The second edge termination structure is arranged in the lateral direction between the first edge termination structure and the side surface and extends from the first surface in a vertical direction more deeply into the semiconductor body than the first edge termination structure.
    Type: Application
    Filed: May 4, 2021
    Publication date: August 19, 2021
    Inventors: Anton Mauder, Hans-Joachim Schulze, Matteo Dainese, Elmar Falck, Franz-Josef Niedernostheide, Manfred Pfaffenlehner
  • Patent number: 11094779
    Abstract: An edge delimits a semiconductor body in a direction parallel to a first side of the semiconductor body. A peripheral area is arranged between the active area and edge. A first semiconductor region of a first conductivity type extends from the active area into the peripheral area. A second semiconductor region of a second conductivity type forms a pn-junction with the first semiconductor region. A first edge termination region of the second conductivity type arranged at the first side adjoins the first semiconductor region, between the second semiconductor region and edge. A second edge termination region of the first conductivity type arranged at the first side and between the first edge termination region and edge has a varying concentration of dopants of the first conductivity type which increases at least next to the first edge termination region substantially linearly with an increasing distance from the first edge termination region.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: August 17, 2021
    Assignee: Infineon Technologies AG
    Inventors: Philip Christoph Brandt, Andre Rainer Stegner, Francisco Javier Santos Rodriguez, Frank Dieter Pfirsch, Hans-Joachim Schulze, Manfred Pfaffenlehner, Thomas Auer