Abstract: A MFMIS memory device is provided with an inverted T-shaped gate stack, which is formed using only one word line mask. The MFMIS memory device is formed using one word line mask, which forms the word line, and using spacers to form an inverted T-shaped gate stack, which is compatible with self-aligned etch processes.

Abstract: A flash memory cell is described, including at least a substrate, a tunnel oxide layer, a floating gate, an insulating layer, a control gate and an inter-gate dielectric layer. The tunnel oxide layer is disposed on the substrate. The floating gate is disposed on the tunnel oxide layer, and is constituted by a first conductive layer on the tunnel oxide layer and a second conductive layer on the first conductive layer. The second conductive layer has a bottom lower than the top surface of the first conductive layer, and has a bowl-like cross section. The insulating layer is disposed between the floating gates, and each control gate is disposed on a floating gate with an inter-gate dielectric layer between them.

Abstract: A MFMIS memory device is provided with an inverted T-shaped gate stack, which is formed using only one word line mask. The MFMIS memory device is formed using one word line mask, which forms the word line, and using spacers to form an inverted T-shaped gate stack, which is compatible with self-aligned etch processes.

Abstract: A MFMIS memory device is provided with an inverted T-shaped gate stack, which is formed using only one word line mask. The MFMIS memory device is formed using one word line mask, which forms the word line, and using spacers to form an inverted T-shaped gate stack, which is compatible with self-aligned etch processes.

Abstract: A flash memory cell is described, including at least a substrate, a tunnel oxide layer, a floating gate, an insulating layer, a control gate and an inter-gate dielectric layer. The tunnel oxide layer is disposed on the substrate. The floating gate is disposed on the tunnel oxide layer, and is constituted by a first conductive layer on the tunnel oxide layer and a second conductive layer on the first conductive layer. The second conductive layer has a bottom lower than the top surface of the first conductive layer, and has a bowl-like cross section. The insulating layer is disposed between the floating gates, and each control gate is disposed on a floating gate with an inter-gate dielectric layer between them.

Abstract: A MFMIS memory device is provided with an inverted T-shaped gate stack, which is formed using only one word line mask. The MFMIS memory device is formed using one word line mask, which forms the word line, and using spacers to form an inverted T-shaped gate stack, which is compatible with self-aligned etch processes.

Abstract: A method of manufacturing DRAM capacitor. An active region is formed above a substrate. A plurality of parallel word lines is formed above the substrate. A first plug and a second plug are formed between the word lines in locations for forming the desired bit line contact and node contact, respectively. Insulation material is deposited into the remaining space between the word lines. A bit line contact is formed above the first plug. A plurality of parallel bit lines is formed above the substrate. The bit lines are perpendicular to the word lines. The bit line is electrically connected to the substrate through the bit line contact and the first plug. The bit lines are electrically insulated from each other. Furthermore, each bit line is covered on top by a hard material layer. Finally, a node contact is formed over the second plug.

Abstract: A fabrication method for a dual damascene structure is described wherein a substrate covered by a HSQ layer is provided. An E-beam curing is conducted on the HSQ layer where the via hole is to be formed. Photolithography and etching are further conducted on the HSQ layer to form a trench. Since the E-beam cured HSQ layer and the thermally cured HSQ layer have a high etching selectively ratio, the HSQ layer that has not been E-beam cured can be wet etched to from a via hole. A dual damascene structure is formed after filling the trench and the via hole with a conductive material, wherein either the via hole or the trench can be first formed.

Abstract: A fabrication method for a self-aligned contact opening involves using polysilicon to protect a cap layer above a conductive line or even a corner of a spacer on a sidewall of the conductive line. A silicon oxide layer is then etched using a conventional silicon oxide etching recipe to form a self-aligned contact opening. This conventional silicon oxide etching recipe not only has a higher etching selectivity for silicon oxide to silicon nitride, but also yields a higher etching selectivity ratio for silicon oxide to polysilicon.