Patents by Inventor Hao-I Yang
Hao-I Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230342272Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.Type: ApplicationFiled: June 28, 2023Publication date: October 26, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hung CHANG, Atul KATOCH, Chia-En HUANG, Ching-Wei WU, Donald G. MIKAN, JR., Hao-I YANG, Kao-Cheng LIN, Ming-Chien TSAI, Saman M.I. ADHAM, Tsung-Yung CHANG, Uppu Sharath CHANDRA
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Publication number: 20230335188Abstract: A memory module with improved timing adaptivity of sensing amplification, comprises at least one sensing amplifier, a tracking word line, a tracking bit line and a pulse-width controller. The tracking word line comprises a front node and an end node. Each said sensing amplifier is enabled/disabled when an enabling signal is activated/deactivated. The pulse-width controller is coupled to the tracking bit line, the front node and the end node. When a voltage of the tracking bit line changes to a predetermined voltage, the pulse-width controller activates the enabling signal, and causes a voltage of the front node to change. When the voltage of the front node changes, the tracking word line causes a voltage of the end node to change after a first delay time. When the voltage of the end node changes, the pulse-width controller deactivates the enabling signal after a second delay time.Type: ApplicationFiled: March 31, 2023Publication date: October 19, 2023Inventors: Po-Yu WU, Hao-I YANG, Nan-Chun LIEN
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Patent number: 11734142Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.Type: GrantFiled: February 18, 2022Date of Patent: August 22, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Donald G. Mikan, Jr., Hao-I Yang, Kao-Cheng Lin, Ming-Chien Tsai, Saman M. I. Adham, Tsung-Yung Chang, Uppu Sharath Chandra
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Patent number: 11677387Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a first inverter, a memory state trigger circuit and a second inverter. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal and a first output clock signal. The memory state latch circuit is configured to latch a second output clock signal responsive to a third output clock signal. The first inverter is configured to generate the first output clock signal responsive to the third output clock signal. The memory state trigger circuit is configured to generate the second output clock signal responsive to the latch output signal. The second inverter is configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.Type: GrantFiled: April 29, 2022Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Yangsyu Lin
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Publication number: 20220255538Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a first inverter, a memory state trigger circuit and a second inverter. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal and a first output clock signal. The memory state latch circuit is configured to latch a second output clock signal responsive to a third output clock signal. The first inverter is configured to generate the first output clock signal responsive to the third output clock signal. The memory state trigger circuit is configured to generate the second output clock signal responsive to the latch output signal. The second inverter is configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.Type: ApplicationFiled: April 29, 2022Publication date: August 11, 2022Inventors: Hao-I YANG, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Yangsyu LIN
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Publication number: 20220171688Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.Type: ApplicationFiled: February 18, 2022Publication date: June 2, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hung CHANG, Atul KATOCH, Chia-En HUANG, Ching-Wei WU, Donald G. MIKAN, JR., Hao-I YANG, Kao-Cheng LIN, Ming-Chien TSAI, Saman M.I. ADHAM, Tsung-Yung CHANG, Uppu Sharath CHANDRA
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Patent number: 11323101Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal or an output clock signal. The memory state latch circuit is configured to generate the output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and configured to adjust the output clock signal responsive to the latch output signal. The clock trigger circuit is coupled to the latch circuit or the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.Type: GrantFiled: March 12, 2021Date of Patent: May 3, 2022Assignee: AIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hao-I Yang, Fu-An Wu, Yangsyu Lin, Chiting Cheng, Cheng Hung Lee, Chen-Lin Yang
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Patent number: 11256588Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.Type: GrantFiled: May 29, 2020Date of Patent: February 22, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Donald G. Mikan, Jr., Hao-I Yang, Kao-Cheng Lin, Ming-Chien Tsai, Saman M. I. Adham, Tsung-Yung Chang, Uppu Sharath Chandra
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Patent number: 11133039Abstract: A power switch control circuit includes a supply rail configured to supply power to a memory array. A first header switch couples the supply rail to a first power supply that corresponds to a first power domain. A second header switch couples the supply rail to a second power supply that corresponds to a second power domain. A control circuit is configured to receive a select signal and a shutdown signal, and to output control signals to the first and second header switches to selectively couple the first and second header switches to the first and second power supplies, respectively, in response to the select signal and the shutdown signal. The control circuit is configured to output the control signals to the first and second header switches to disconnect both the first and second header switches from the first and second power supplies in response to the shutdown signal and irrespective of the select signal.Type: GrantFiled: October 7, 2019Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Yu-Hao Hsu
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Publication number: 20210203312Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal or an output clock signal. The memory state latch circuit is configured to generate the output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and configured to adjust the output clock signal responsive to the latch output signal. The clock trigger circuit is coupled to the latch circuit or the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.Type: ApplicationFiled: March 12, 2021Publication date: July 1, 2021Inventors: Hao-I YANG, Fu-An WU, Yangsyu LIN, Chiting CHENG, Cheng Hung LEE, Chen-Lin YANG
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Patent number: 10951200Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal. The memory state latch circuit is coupled to the latch circuit, and generates an output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and adjusts the output clock signal responsive to the latch output signal or a reset signal. The clock trigger circuit is coupled to the latch circuit and the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.Type: GrantFiled: February 25, 2020Date of Patent: March 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Yangsyu Lin
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Publication number: 20200293417Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.Type: ApplicationFiled: May 29, 2020Publication date: September 17, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hung CHANG, Atul KATOCH, Chia-En HUANG, Ching-Wei WU, Donald G. MIKAN, JR., Hao-I YANG, Kao-Cheng LIN, Ming-Chien TSAI, Saman M.I. ADHAM, Tsung-Yung CHANG, Uppu Sharath CHANDRA
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Patent number: 10705934Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.Type: GrantFiled: September 11, 2017Date of Patent: July 7, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hung Chang, Atul Katoch, Chia-En Huang, Ching-Wei Wu, Donald G. Mikan, Jr., Hao-I Yang, Kao-Cheng Lin, Ming-Chien Tsai, Saman M. I. Adham, Tsung-Yung Chang, Uppu Sharath Chandra
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Publication number: 20200195236Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal. The memory state latch circuit is coupled to the latch circuit, and generates an output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and adjusts the output clock signal responsive to the latch output signal or a reset signal. The clock trigger circuit is coupled to the latch circuit and the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Inventors: Hao-I YANG, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Yangsyu LIN
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Publication number: 20200118602Abstract: A power switch control circuit includes a supply rail configured to supply power to a memory array. A first header switch couples the supply rail to a first power supply that corresponds to a first power domain. A second header switch couples the supply rail to a second power supply that corresponds to a second power domain. A control circuit is configured to receive a select signal and a shutdown signal, and to output control signals to the first and second header switches to selectively couple the first and second header switches to the first and second power supplies, respectively, in response to the select signal and the shutdown signal. The control circuit is configured to output the control signals to the first and second header switches to disconnect both the first and second header switches from the first and second power supplies in response to the shutdown signal and irrespective of the select signal.Type: ApplicationFiled: October 7, 2019Publication date: April 16, 2020Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Yu-Hao Hsu
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Patent number: 10574213Abstract: A clock circuit includes a first latch circuit, second latch circuit, first trigger circuit and second trigger circuit. The first latch circuit is configured to generate a first latch output signal based on at least a trigger signal or an output clock signal. The second latch circuit is coupled to the first latch circuit, and configured to generate the output clock signal responsive to a control signal. The first trigger circuit is coupled to the second latch circuit, and configured to adjust the output clock signal responsive to at least the first latch output signal. The second trigger circuit is coupled to the first latch circuit and the first trigger circuit by a first node, configured to generate the trigger signal responsive to an input clock signal, and configured to control the first latch circuit and the first trigger circuit based on at least the trigger signal.Type: GrantFiled: November 30, 2018Date of Patent: February 25, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Yangsyu Lin
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Patent number: 10340897Abstract: A clock circuit includes a first latch, second latch, first trigger circuit and clock trigger circuit. The first latch generates a first latch output signal based on a first control signal, an enable signal and an output clock signal. The second latch is coupled to the first latch, and configured to generate the output clock signal responsive to a second control signal. The first trigger circuit is coupled to the first latch and the second latch, and configured to adjust the output clock signal responsive to at least the first latch output signal or a reset signal. The clock trigger circuit is coupled to the first latch and the first trigger circuit by a first node, is configured to generate the first control signal responsive to an input clock signal, and configured to control the first latch and the first trigger circuit based on at least the first control signal.Type: GrantFiled: July 19, 2018Date of Patent: July 2, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hao-I Yang, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Yangsyu Lin
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Patent number: 10276232Abstract: A sense amplify enable (SAE) signal is generated on a SAE line by receiving a trigger signal at a first circuit portion coupled to a first domain power supply and a second circuit portion coupled to a second domain power supply. The second domain power supply is separate and distinct from the first domain power supply. The first circuit portion and the second circuit portion are each further coupled to the SAE line for carrying the SAE signal. For a first period of time, a first portion of the SAE signal is generated based on the first domain power supply using the first circuit portion. And, for second period of time, a second portion of the SAE signal is generated based on the second domain power supply using a second circuit portion.Type: GrantFiled: January 3, 2018Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hao-I Yang, Tsung-Hsien Huang
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Publication number: 20190103858Abstract: A clock circuit includes a first latch circuit, second latch circuit, first trigger circuit and second trigger circuit. The first latch circuit is configured to generate a first latch output signal based on at least a trigger signal or an output clock signal. The second latch circuit is coupled to the first latch circuit, and configured to generate the output clock signal responsive to a control signal. The first trigger circuit is coupled to the second latch circuit, and configured to adjust the output clock signal responsive to at least the first latch output signal. The second trigger circuit is coupled to the first latch circuit and the first trigger circuit by a first node, configured to generate the trigger signal responsive to an input clock signal, and configured to control the first latch circuit and the first trigger circuit based on at least the trigger signal.Type: ApplicationFiled: November 30, 2018Publication date: April 4, 2019Inventors: Hao-I YANG, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Yangsyu LIN
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Publication number: 20190036513Abstract: A clock circuit includes a first latch, second latch, first trigger circuit and clock trigger circuit. The first latch generates a first latch output signal based on a first control signal, an enable signal and an output clock signal. The second latch is coupled to the first latch, and configured to generate the output clock signal responsive to a second control signal. The first trigger circuit is coupled to the first latch and the second latch, and configured to adjust the output clock signal responsive to at least the first latch output signal or a reset signal. The clock trigger circuit is coupled to the first latch and the first trigger circuit by a first node, is configured to generate the first control signal responsive to an input clock signal, and configured to control the first latch and the first trigger circuit based on at least the first control signal.Type: ApplicationFiled: July 19, 2018Publication date: January 31, 2019Inventors: Hao-I YANG, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Yangsyu LIN