Patents by Inventor Hao-Jan Chao
Hao-Jan Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9057763Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: GrantFiled: November 12, 2013Date of Patent: June 16, 2015Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaqing Wen
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Patent number: 9026875Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: GrantFiled: May 15, 2013Date of Patent: May 5, 2015Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaqing Wen
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Patent number: 8769359Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: GrantFiled: November 12, 2013Date of Patent: July 1, 2014Assignee: Syntest Technologies, Inc.Inventors: Luang-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaqing Wen
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Publication number: 20140082446Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: ApplicationFiled: November 12, 2013Publication date: March 20, 2014Applicant: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaqing Wen
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Publication number: 20140075256Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: ApplicationFiled: November 12, 2013Publication date: March 13, 2014Applicant: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaqing Wen
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Publication number: 20130268818Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: ApplicationFiled: May 15, 2013Publication date: October 10, 2013Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaqing Wen
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Patent number: 8458544Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, includes the steps of: (a) generating and shifting-in N test stimuli to all scan cells within the N clock domains during a shift-in operation; (b) applying an ordered sequence of capture clocks to all scan cells within the N clock domains, the ordered sequence of capture clocks including a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all scan cells to locate any faults therein.Type: GrantFiled: December 2, 2011Date of Patent: June 4, 2013Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Hao-Jan Chao, Shianling Wu
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Publication number: 20120166903Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, includes the steps of: (a) generating and shifting-in N test stimuli to all scan cells within the N clock domains during a shift-in operation; (b) applying an ordered sequence of capture clocks to all scan cells within the N clock domains, the ordered sequence of capture clocks including a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all scan cells to locate any faults therein.Type: ApplicationFiled: December 2, 2011Publication date: June 28, 2012Applicant: Syntest Technologies, Inc.Inventors: Laung-Terng WANG, Hao-Jan CHAO, Shianling WU
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Patent number: 8091002Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: GrantFiled: June 9, 2010Date of Patent: January 3, 2012Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Shianling Wu, Zhigang Jiang, Jinsong Liu, Hao-Jan Chao, Lizhen Yu, Feifei Zhao, Fangfang Li, Jianping Yan
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Publication number: 20100287430Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.Type: ApplicationFiled: June 9, 2010Publication date: November 11, 2010Applicant: Syntest Technologies, Inc.Inventors: Laung-Terng WANG, Shianling Wu, Zhigang Jiang, Jinsong Liu, Hao-Jan Chao, Lizhen Yu, Feifei Zhao, Fangfang Li, Jianping Yan
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Patent number: 7779323Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.Type: GrantFiled: August 20, 2008Date of Patent: August 17, 2010Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaoqing Wen
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Publication number: 20100138709Abstract: A hybrid clocking scheme for simultaneously detecting a b-cycle path-delay fault in a b-cycle (false) path and a c-cycle path-delay fault in a c-cycle (false) path using at least n+1 at-speed clock pulses during a capture operation in a clock domain in a scan design or a scan-based BIST design, where 1<=b<=c<=n. The scan design or BIST design includes multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The design includes one or more clock domains each running at its intended operating frequency or at-speed. The hybrid clocking scheme comprises at least one at-speed shift clock pulse or one at-speed capture clock pulse immediately followed by at least two at-speed capture clock pulses during the capture operation to simultaneously detect the b-cycle path-delay fault and the c-cycle path-delay fault within the clock domain.Type: ApplicationFiled: September 4, 2009Publication date: June 3, 2010Inventors: Laung-Terng WANG, Michael S. Hsiao, Hao-Jan Chao, Zhigang Jiang, Shianling Wu, Jianping Yan
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Publication number: 20090132880Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.Type: ApplicationFiled: August 20, 2008Publication date: May 21, 2009Inventors: Laung-Terng (L.- T.) Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaoqing Wen
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Patent number: 7284175Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.Type: GrantFiled: November 22, 2006Date of Patent: October 16, 2007Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Ming-Tung Chang, Hao-Jan Chao, Xiaoqing Wen, Po-Ching Hsu
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Publication number: 20070168803Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.Type: ApplicationFiled: November 22, 2006Publication date: July 19, 2007Inventors: Laung-Terng Wang, Ming-Tung Chang, Hao-Jan Chao, Xiaoqing Wen, Po-Ching Hsu
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Patent number: 7191373Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.Type: GrantFiled: February 27, 2002Date of Patent: March 13, 2007Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng (L.-T.) Wang, Ming-Tung Chang, Shyh-Horng Lin, Hao-Jan Chao, Jaehee Lee, Hsin-Po Wang, Xiaoqing Wen, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Sen-Wei Tsai, Chi-Chan Hsu
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Patent number: 7058869Abstract: A method and apparatus for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit where scan chains embedded in a scan core 303 have no external access, such as the case when they are surrounded by pattern generators 302 and pattern compactors 305, using a DFT (design-for-test) technology such as Logic BIST (built-in self-test) or Compressed Scan. This invention includes an output-mask controller 301 and an output-mask network 304 to allow designers to mask off selected scan cells 311 from being compacted in a selected pattern compactor 305. This invention also includes an input chain-mask controller and an input-mask network for driving constant logic values into scan chain inputs of selected scan chains to allow designers to recover from scan chain hold time violations.Type: GrantFiled: January 23, 2004Date of Patent: June 6, 2006Assignee: Syntest Technologies, Inc.Inventors: Khader S. Abdel-Hafez, Xiaoqing Wen, Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Hao-Jan Chao, Hsin-Po Wang
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Patent number: 7007213Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.Type: GrantFiled: February 7, 2002Date of Patent: February 28, 2006Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng (L.-T.) Wang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Hsin-Po Wang, Hao-Jan Chao, Xiaoqing Wen
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Publication number: 20040237015Abstract: A method and apparatus for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit where scan chains embedded in a scan core 303 have no external access, such as the case when they are surrounded by pattern generators 302 and pattern compactors 305, using a DFT (design-for-test) technology such as Logic BIST (built-in self-test) or Compressed Scan. This invention includes an output-mask controller 301 and an output-mask network 304 to allow designers to mask off selected scan cells 311 from being compacted in a selected pattern compactor 305. This invention also includes an input chain-mask controller and an input-mask network for driving constant logic values into scan chain inputs of selected scan chains to allow designers to recover from scan chain hold time violations.Type: ApplicationFiled: January 23, 2004Publication date: November 25, 2004Inventors: Khader S. Abdel-Hafez, Xiaoqing Wen, Laung-Terng Wang, Po-Ching Hsu, Shih-Chia Kao, Hao-Jan Chao, Hsin-Po Wang
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Publication number: 20020138801Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.Type: ApplicationFiled: February 27, 2002Publication date: September 26, 2002Inventors: Laung-Terng Wang, Ming-Tung Chang, Shyh-Horng Lin, Hao-Jan Chao, Jaehee Lee, Hsin-Po Wang, Xiaoqing Wen, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Sen-Wei Tsai, Chi-Chan Hsu